Abstract: Charging system and method using a motor driving system are proposed. The charging system includes a battery, an inverter to which D.C. power stored in the battery is applied, including a plurality of legs each including two switching elements, a motor including a plurality of coils of which first ends are respectively connected to connection nodes of the switching elements of each of the plurality of legs, and second ends are connected to each other to form a neutral point, and an inverter driving part configured to control switching of the switching elements, so that switching speeds of the switching elements are different for each mode of a motor driving mode and a charging mode so as to change magnitude of charging voltage supplied to the neutral point of the motor and to output the charging voltage to the battery.

Abstract: A Unified Speech and Audio Codec (USAC) that may process a window sequence based on mode switching is provided. The USAC may perform encoding or decoding by overlapping between frames based on a folding point when mode switching occurs. The USAC may process different window sequences for each situation to perform encoding or decoding, and thereby may improve a coding efficiency.

Abstract: A semiconductor memory device, a power decoupling capacitor array thereof, and a memory system including the same are disclosed. The semiconductor memory device includes a memory cell array, a peripheral circuit, and a plurality of power decoupling capacitor arrays. The memory cell array includes a plurality of memory cells, and each of the plurality of memory cells includes a cell capacitor. Each of the plurality of power decoupling capacitor arrays includes m×n power decoupling capacitor sub arrays in an m×n matrix form. Each of the m×n power decoupling capacitor sub arrays includes a plurality of power decoupling capacitors, and each of the plurality of power decoupling capacitors has the same structure as the cell capacitor and the plurality of power decoupling capacitors are connected in parallel.

Abstract: The present invention relates to a side mirror for a vehicle, the side mirror being provided on a vehicle for facilitating the checking of road situations on the left, right, and rear sides. The side mirror for a vehicle comprises a mirror housing which is mounted on the exterior of the vehicle, and a mirror part which is supported by the mirror housing, and is divided into multiple mirror areas which are in aspherical form respectively across the horizontal direction from the internal side, which is close to the vehicle, to the external side, which is far from the vehicle. In the mirror part, the respective optical powers of the mirror areas gradually increase from the internal side to the external side so as to have the same optical power at the borders of the mirror areas, and the optical power rate for at least one of the mirror areas is constant.

Abstract: Provided is a method for detecting an application in a wireless communication system. The method includes receiving and inspecting a packet; detecting flows from the packet using a predefined signature; granting a score to each of the detected flows, and summing the granted scores by integrating the detected flows for each application; comparing the summed score of the flows integrated for each application with a preset value; and determining that an application is detected, if the summed score is greater than the preset value.

Abstract: The present invention relates to a side mirror for a vehicle, the side mirror being provided on a vehicle for facilitating the checking of road situations on the left, right, and rear sides. The side mirror for a vehicle comprises a mirror housing which is mounted on the exterior of the vehicle, and a mirror part which is supported by the mirror housing, and is divided into multiple mirror areas which are in aspherical form respectively across the horizontal direction from the internal side, which is close to the vehicle, to the external side, which is far from the vehicle. In the mirror part, the respective optical powers of the mirror areas gradually increase from the internal side to the external side so as to have the same optical power at the borders of the mirror areas, and the optical power rate for at least one of the mirror areas is constant.

Abstract: Provided is a method for detecting an application in a wireless communication system. The method includes receiving and inspecting a packet; detecting flows from the packet using a predefined signature; granting a score to each of the detected flows, and summing the granted scores by integrating the detected flows for each application; comparing the summed score of the flows integrated for each application with a preset value; and determining that an application is detected, if the summed score is greater than the preset value.

Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract: A stacked layer type semiconductor device includes N memories each including at least one main via and (N?1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1.

Abstract: A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.

Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract: A semiconductor device, memory device, system, and method of using a stacked structure for stably transmitting signals among a plurality of semiconductor layers is disclosed. The device includes at least a first semiconductor chip including a first temperature sensor circuit configured to output first temperature information related to the first semiconductor chip, and at least one through substrate via.

Abstract: Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls.

Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.

Abstract: Provided are a semiconductor chip including a TSV passing through a transistor, and a stack module and a memory card using such a semiconductor chip. The semiconductor chip may include a semiconductor layer that has a first surface and a second surface opposite to each other. A conductive layer may be disposed on the first surface of the semiconductor layer. A TSV may pass through the semiconductor layer and the conductive layer. A side wall insulating layer may surround a side wall of the TSV in order to electrically insulate the semiconductor layer and the conductive layer from the TSV.

Abstract: A method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors includes controlling the deep power down mode in the multi-port semiconductor memory such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

Abstract: Provided is a stacked semiconductor device including n stacked chips. Each chip includes “j” corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip.

Abstract: A memory device includes a memory cell array, a column decoder, and a row decoder. The row decoder includes a first word line driver and a second word line driver. The first word line driver is configured to electrically coupled to a first set of antifuse memory cells coupled to a first word line. The second word line driver is configured to electrically coupled to a second set of antifuse memory cells coupled to a second word line. The first set of antifuse memory cells are arranged in first and third rows of the memory cell array, and the second set of antifuse memory cells are arranged in second and fourth rows of the memory cell array. The second row is arranged between the first and third rows.

Abstract: A stacked layer type semiconductor device includes N memories each including at least one main via and (N?1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1.

Abstract: A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.