Patents by Inventor Hoi Ju CHUNG

Hoi Ju CHUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220121518
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Application
    Filed: December 27, 2021
    Publication date: April 21, 2022
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
  • Patent number: 11239960
    Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-ju Chung, Sang-Uhn Cha, Hyun-Joong Kim
  • Patent number: 11231996
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
  • Publication number: 20210397515
    Abstract: A method for operating a memory includes: reading data and an error correction code from a memory core; correcting an error of the read data based on the read error correction code to produce error-corrected data; generating new data by replacing a portion of the error-corrected data with write data, the portion becoming a write data portion; generating a new error correction code based on the new data; and writing the write data portion of the new data and the new error correction code into the memory core.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 23, 2021
    Inventors: Munseon JANG, Hoi Ju CHUNG, Jang Ryul KIM
  • Publication number: 20210149764
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Application
    Filed: December 30, 2020
    Publication date: May 20, 2021
    Inventors: HOI-JU CHUNG, SANG-UHN CHA, HO-YOUNG SONG, HYUN-JOONG KIM
  • Patent number: 10929225
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
  • Publication number: 20210044393
    Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-ju CHUNG, Sang-Uhn CHA, Hyun-Joong KIM
  • Patent number: 10855412
    Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Hyun-Joong Kim
  • Publication number: 20200301779
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: HOI-JU CHUNG, SANG-UHN CHA, HO-YOUNG SONG, HYUN-JOONG KIM
  • Patent number: 10705908
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
  • Patent number: 10684793
    Abstract: A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoi-ju Chung, Su-a Kim, Mu-jin Seo, Hak-soo Yu, Jae-youn Youn, Hyo-jin Choi
  • Publication number: 20190288805
    Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 19, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju CHUNG, Sang-Uhn CHA, Hyun-Joong KIM
  • Patent number: 10355833
    Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Hyun-Joong Kim
  • Patent number: 10255989
    Abstract: A semiconductor memory device includes a memory cell array and a main controller. The memory cell array includes a plurality of memory bank arrays, and each of the memory bank arrays includes a plurality of pages. The main controller counts a number of accesses to a first memory region of the memory cell array, generates at least one victim address of at least one neighbor memory region that is adjacent to the first memory region and performs a scrubbing operation sub-pages of the pages corresponding to the at least one victim address when the counted number of accesses reaches a first reference value during a reference interval.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: April 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hoi-Ju Chung
  • Patent number: 10198221
    Abstract: A method of scrubbing errors from a semiconductor memory device including a memory cell array and an error correction circuit, can be provided by accessing a page of the memory cell array to provide a data that includes sub units that are separately writable to the page of memory and to provide parity data configured to detect and correct a bit error in the data and selectively enabling write-back of a selected sub unit of the data responsive to determining that the selected sub unit of data includes a correctable error upon access as part of an error scrubbing operation.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Uhn Cha, Hoi-Ju Chung, Uk-Song Kang
  • Patent number: 10191805
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit performs an error correction code (ECC) encoding on write data to be stored in the memory cell array, and performs an ECC decoding on read data from the memory cell array. The control logic circuit controls access to the memory cell array and generates an engine configuration selection signal based on a command. The error correction circuit reconfigures a number of units for which ECC including the ECC encoding and the ECC decoding is performed, in response to the engine configuration selection signal.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hoi-Ju Chung
  • Patent number: 10156995
    Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: December 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Hoi-Ju Chung, Ye-Sin Ryu, Seong-Jin Cho
  • Patent number: 10127974
    Abstract: Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Joong Kim, Ho-young Song, Hoi-ju Chung, Ju-yun Jung, Sang-uhn Cha
  • Patent number: 10127102
    Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ye-Sin Ryu, Hoi-Ju Chung, Sang-Uhn Cha, Young-Yong Byun, Seong-Jin Jang
  • Publication number: 20180323915
    Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
    Type: Application
    Filed: July 11, 2018
    Publication date: November 8, 2018
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Hyun-Joong Kim