Abstract: A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address.

Abstract: A memory device using error correcting code and a system including the same are provided. The memory system includes a memory device, and a storage block connected to the memory device. The memory device includes a normal cell region including a first plurality of memory cells for storing data bits, and an error correcting code (ECC) cell region including a second plurality of memory cells for storing first through mth sets of ECC bits. The storage block includes a third plurality of memory cells for storing first through nth sets of the ECC bits. Each memory cell of the first and second plurality of memory cells is a first type of memory cell and each memory cell of the third plurality of memory cells is a second type of memory cell different from the first type of memory cell.

Abstract: A memory device using error correcting code and a system including the same are provided. The memory device includes a memory cell array including a plurality of bit lines and a plurality of memory cells; an access block for accessing the memory cell array; and a controller block for receiving a first operation command signal, dividing the first operation command signal into at least two paths pulse signals corresponding to at least two paths, based on a pre-determined criterion, and then supplying the at least two path pulse signals to the access block. The access block operates based on an output signal of the controller block.

Abstract: In one embodiment, a memory device includes a plurality of unit cell arrays. Each unit cell array includes an array of memory cells arranged in a plurality of columns, and each column is associated with a bit line. The memory device further includes a program control circuit configured to program cells in the plurality of unit cell arrays based on program bits associated with the plurality of unit cell arrays. For example, the program control unit is configured to simultaneously program one memory cell in each unit cell array having at least one associated program bit.

Abstract: A nonvolatile memory device that employs a variable resistive element includes: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at one side of the memory cell array and performs a first operation on the memory cells; a second circuit block that is disposed at the other side of the memory cell array and performs a second operation on the memory cells, wherein the second operation is different from the first operation; and a redundancy block that is disposed closer to the second circuit block than the first circuit block, and which compares a repair address of a repaired memory cell among the plurality of memory cells with an input address to then generate a redundancy control signal, and to supply the redundancy control signal to the first circuit block and the second circuit block.

Abstract: A semiconductor device includes phase-change memory cells and an access circuit. The access circuit generates a plurality of bitwise comparison signals indicating different comparison events for respective write and read bit groups. At least a portion of the write data is then written to the phase-change memory cells according to a number of activated comparison signals for each comparison event, as well as according to a ratio of a set current pulse width and a reset current pulse width as applied to the of phase-change memory cells.

Abstract: A nonvolatile memory device is provided, which includes a memory core including a plurality of nonvolatile memory cells, a first read circuit that reads a first codeword from the memory core during a Read While Write (RWW) operation, a second read circuit that reads a second codeword from the memory core during a Read Modification Write (RMW) operation, and a common decoder that is shared by the first read circuit and the second read circuit and selectively decodes the first codeword or the second codeword.

Abstract: A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address.

Abstract: A memory device using error correcting code and a system including the same are provided. The memory device includes a memory cell array including a plurality of bit lines and a plurality of memory cells; an access block for accessing the memory cell array; and a controller block for receiving a first operation command signal, dividing the first operation command signal into at least two paths pulse signals corresponding to at least two paths, based on a pre-determined criterion, and then supplying the at least two path pulse signals to the access block. The access block operates based on an output signal of the controller block.

Abstract: A memory device using error correcting code and a system including the same are provided. The memory system includes a memory device, and a storage block connected to the memory device. The memory device includes a normal cell region including a first plurality of memory cells for storing data bits, and an error correcting code (ECC) cell region including a second plurality of memory cells for storing first through mth sets of ECC bits. The storage block includes a third plurality of memory cells for storing first through nth sets of the ECC bits. Each memory cell of the first and second plurality of memory cells is a first type of memory cell and each memory cell of the third plurality of memory cells is a second type of memory cell different from the first type of memory cell.

Abstract: In one embodiment, a memory device includes a plurality of unit cell arrays. Each unit cell array includes an array of memory cells arranged in a plurality of columns, and each column is associated with a bit line. The memory device further includes a program control circuit configured to program cells in the plurality of unit cell arrays based on program bits associated with the plurality of unit cell arrays. For example, the program control unit is configured to simultaneously program one memory cell in each unit cell array having at least one associated program bit.

Abstract: A nonvolatile memory device that employs a variable resistive element includes: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at one side of the memory cell array and performs a first operation on the memory cells; a second circuit block that is disposed at the other side of the memory cell array and performs a second operation on the memory cells, wherein the second operation is different from the first operation; and a redundancy block that is disposed closer to the second circuit block than the first circuit block, and which compares a repair address of a repaired memory cell among the plurality of memory cells with an input address to then generate a redundancy control signal, and to supply the redundancy control signal to the first circuit block and the second circuit block.

Abstract: A semiconductor device includes phase-change memory cells and an access circuit. The access circuit generates a plurality of bitwise comparison signals indicating different comparison events for respective write and read bit groups. At least a portion of the write data is then written to the phase-change memory cells according to a number of activated comparison signals for each comparison event, as well as according to a ratio of a set current pulse width and a reset current pulse width as applied to the of phase-change memory cells.