Patents by Inventor Hokyun Ahn
Hokyun Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140159115Abstract: A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate and a head portion of the T-type gate electrode such that a portion of the third insulating layer is in contact with a foot portion of the T-type gate electrode. The second insulating layer is disposed between the substrate and the head portion of the T-type gate electrode to be in contact with the third insulating layer. The first insulating layer and another portion of the third insulating layer are sequentially stacked between the substrate and the head portion of the T-type gate electrode to be in contact with the second insulating layer.Type: ApplicationFiled: June 3, 2013Publication date: June 12, 2014Inventors: Jong-Won LIM, Hokyun AHN, Woojin Chang, Dong Min Kang, Seong-II Kim, Sang-Heung Lee, Hyung Sup Yoon, Chull Won Ju, Hae Cheon Kim, Jae Kyoung Mun, Eun Soo Nam
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Publication number: 20140159049Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.Type: ApplicationFiled: May 30, 2013Publication date: June 12, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Sang Choon KO, Jae Kyoung Mun, Byoung-Gue Min, Young Rak Park, Hokyun Ahn, Jeong-Jin Kim, Eun Soo Nam
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Publication number: 20140159050Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a ?-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the ?-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.Type: ApplicationFiled: July 3, 2013Publication date: June 12, 2014Inventors: Hyung Sup YOON, Byoung-Gue Min, Jong-Won Lim, Hokyun Ahn, Seong-ll Kim, Sang-Heung Lee, Dong Min Kang, Chull Won Ju, Jae Kyoung Mun
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Publication number: 20140103539Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.Type: ApplicationFiled: September 9, 2013Publication date: April 17, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Byoung-Gue MIN, Sang Choon KO, Jong-Won Lim, Hokyun AHN, Hyung Sup YOON, Jae Kyoung MUN, Eun Soo NAM
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Publication number: 20140035044Abstract: Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.Type: ApplicationFiled: October 9, 2013Publication date: February 6, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Hokyun AHN, Jong-Won LIM, Hyung Sup YOON, Byoung-Gue MIN, Sang-Heung LEE, Hae Cheon KIM, Eun Soo NAM
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Patent number: 8609474Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device.Type: GrantFiled: October 17, 2011Date of Patent: December 17, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Jong-Won Lim, Hokyun Ahn, Dong Min Kang, Woojin Chang, Hae Cheon Kim, Eun Soo Nam
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Patent number: 8586462Abstract: Disclosed are a method of manufacturing a field-effect transistor. The disclosed method includes: providing a semiconductor substrate; forming a source ohmic metal layer on one side of the semiconductor substrate; forming a drain ohmic metal layer on another side of the semiconductor substrate; forming a gate electrode between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; forming an insulating film on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and forming a plurality of field electrodes on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.Type: GrantFiled: November 30, 2011Date of Patent: November 19, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Hokyun Ahn, Jong-Won Lim, Hyung Sup Yoon, Byoung-Gue Min, Sang-Heung Lee, Hae Cheon Kim, Eun Soo Nam
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Patent number: 8518794Abstract: Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall.Type: GrantFiled: September 1, 2010Date of Patent: August 27, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Hokyun Ahn, Jong-Won Lim, Hyung Sup Yoon, Woojin Chang, Hae Cheon Kim
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Patent number: 8338241Abstract: Provided are a method of manufacturing a normally-off mode high frequency device structure and a method of simultaneously manufacturing a normally-on mode high frequency device structure and a normally-off mode high frequency device structure on a single substrate.Type: GrantFiled: October 28, 2011Date of Patent: December 25, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Hyung Sup Yoon, Byoung-Gue Min, Hokyun Ahn, Sang-Heung Lee, Hae Cheon Kim
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Patent number: 8294521Abstract: Provided is a power amplifier including: a depletion mode high electron mobility transistor (D-mode HEMT) configured to amplify a signal inputted to a gate terminal and output the amplified signal through a drain terminal; an input matching circuit configured to serially ground the gate terminal; and a DC bias circuit connected between the drain terminal and a ground. Through the foregoing configuration, the HEMT may be biased only by a single DC bias circuit without any biasing means to provide a negative voltage. Also, superior matching characteristic may be provided in various operation frequency bands through a shunt inductor and a choke inductor.Type: GrantFiled: August 12, 2010Date of Patent: October 23, 2012Assignee: Electronics and Telecommunications Research InstituteInventors: Dong Min Kang, Hong Gu Ji, Hokyun Ahn, Jong-Won Lim, Woojin Chang, Sang-Heung Lee, Dong-Young Kim, Hae Cheon Kim
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Publication number: 20120153361Abstract: Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.Type: ApplicationFiled: November 30, 2011Publication date: June 21, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hokyun Ahn, Jong-Won Lim, Hyung Sup Yoon, Byoung-Gue Min, Sang-Heung Lee, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20120146107Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device.Type: ApplicationFiled: October 17, 2011Publication date: June 14, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jong-Won LIM, Hokyun Ahn, Dong Min Kang, Woojin Chang, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20120142148Abstract: Provided are a method of manufacturing a normally-off mode high frequency device structure and a method of simultaneously manufacturing a normally-on mode high frequency device structure and a normally-off mode high frequency device structure on a single substrate.Type: ApplicationFiled: October 28, 2011Publication date: June 7, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyung Sup YOON, Byoung-Gue Min, Hokyun Ahn, Sang-Heung Lee, Hae Cheon Kim
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Patent number: 8058658Abstract: Provided is a high-speed optical interconnection device. The high-speed optical interconnection device includes a first semiconductor chip, light emitters, optical detectors, and a second semiconductor chip, which are disposed on a silicon-on-insulator (SOI) substrate. The light emitters receive electrical signals from the first semiconductor chip to output optical signals. The optical detectors detect the optical signals to convert the optical signals into electrical signals. The second semiconductor chip receives the electrical signals converted by the optical detectors.Type: GrantFiled: April 9, 2009Date of Patent: November 15, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Sang-Heung Lee, Hae Cheon Kim, Dong Min Kang, Dong-Young Kim, Jae Kyoung Mun, Hokyun Ahn, Jong-Won Lim, Woo Jin Chang, Hong Gu Ji, Eun Soo Nam
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Patent number: 8053345Abstract: Provided is a method for fabricating a field effect transistor. In the method, an active layer and a capping layer are formed on a substrate. A source electrode and a drain electrode is formed on the capping layer. A dielectric interlayer is formed on the substrate, and resist layers having first and second openings with asymmetrical depths are formed on the dielectric interlayer between the source electrode and the drain electrode. The first opening exposes the dielectric interlayer, and the second opening exposes the lowermost of the resist layers. The dielectric interlayer in the bottom of the first opening and the lowermost resist layer under the second opening are simultaneously removed to expose the capping layer to the first opening and expose the dielectric interlayer to the second opening. The capping layer of the first opening is removed to expose the active layer.Type: GrantFiled: May 4, 2010Date of Patent: November 8, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Hokyun Ahn, Jong-Won Lim, Hyung Sup Yoon, Woojin Chang, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20110143505Abstract: Provided is a method for fabricating a field effect transistor. In the method, an active layer and a capping layer are formed on a substrate. A source electrode and a drain electrode is formed on the capping layer. A dielectric interlayer is formed on the substrate, and resist layers having first and second openings with asymmetrical depths are formed on the dielectric interlayer between the source electrode and the drain electrode. The first opening exposes the dielectric interlayer, and the second opening exposes the lowermost of the resist layers. The dielectric interlayer in the bottom of the first opening and the lowermost resist layer under the second opening are simultaneously removed to expose the capping layer to the first opening and expose the dielectric interlayer to the second opening. The capping layer of the first opening is removed to expose the active layer.Type: ApplicationFiled: May 4, 2010Publication date: June 16, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hokyun AHN, Jong-Won Lim, Hyung Sup Yoon, Woojin Chang, Hae Cheon Kim, Eun Soo Nam
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Publication number: 20110057237Abstract: Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall.Type: ApplicationFiled: September 1, 2010Publication date: March 10, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hokyun AHN, Jong-Won Lim, Hyung Sup Yoon, Woojin Chang, Hae Cheon Kim
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Publication number: 20110037521Abstract: Provided is a power amplifier including: a depletion mode high electron mobility transistor (D-mode HEMT) configured to amplify a signal inputted to a gate terminal and output the amplified signal through a drain terminal; an input matching circuit configured to serially ground the gate terminal; and a DC bias circuit connected between the drain terminal and a ground. Through the foregoing configuration, the HEMT may be biased only by a single DC bias circuit without any biasing means to provide a negative voltage. Also, superior matching characteristic may be provided in various operation frequency bands through a shunt inductor and a choke inductor.Type: ApplicationFiled: August 12, 2010Publication date: February 17, 2011Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Dong Min KANG, Hong Gu JI, Hokyun AHN, Jong-Won LIM, Woojin CHANG, Sang-Heung LEE, Dong-Young KIM, Hae Cheon KIM
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Publication number: 20100133551Abstract: Provided is a high-speed optical interconnection device. The high-speed optical interconnection device includes a first semiconductor chip, light emitters, optical detectors, and a second semiconductor chip, which are disposed on a silicon-on-insulator (SOI) substrate. The light emitters receive electrical signals from the first semiconductor chip to output optical signals. The optical detectors detect the optical signals to convert the optical signals into electrical signals. The second semiconductor chip receives the electrical signals converted by the optical detectors.Type: ApplicationFiled: April 9, 2009Publication date: June 3, 2010Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang-Heung Lee, Hae Cheon Kim, Dong Min Kang, Dong-Young Kim, Jae-Kyoung Mun, Hokyun Ahn, Jong-Won Lim, Woo Jin Chang, Hong Gu Ji, Eun Soo Nam
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Patent number: 6979871Abstract: A semiconductor device in which a silica aerogel layer having a very low dielectric constant is used as an insulating layer such that parasitic capacitance between a gate electrode and a source electrode in a field effect transistor having a T-shaped gate electrode, and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, source and drain electrodes, which are formed on the semiconductor substrate to make ohmic contact with the semiconductor substrate, a T-shaped gate electrode, which is formed between the source and drain electrodes on the semiconductor substrate, and an insulating layer including a silica aerogel layer, the silica aerogel layer being interposed between the gate electrode and the source and drain electrodes.Type: GrantFiled: November 25, 2003Date of Patent: December 27, 2005Assignee: Electronics and Telecommunications Research InstituteInventors: Hokyun Ahn, Jae Kyoung Mun, Haecheon Kim