Patents by Inventor Hong-Bae Park
Hong-Bae Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160133632Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.Type: ApplicationFiled: September 14, 2015Publication date: May 12, 2016Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
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Patent number: 9287199Abstract: Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.Type: GrantFiled: December 20, 2010Date of Patent: March 15, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-Lan Lee, Hong-Bae Park, Sang-Jin Hyun, Yu-Gyun Shin, Sug-Hun Hong, Hoon-Joo Na, Hyung-Seok Hong
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Patent number: 9252058Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping.Type: GrantFiled: June 19, 2014Date of Patent: February 2, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-Seok Hong, Sang-Jin Hyun, Hong-Bae Park, Hoon-Joo Na, Hye-Lan Lee
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Patent number: 9240483Abstract: A semiconductor device includes a fin-type active region; a gate dielectric layer covering an upper surface and opposite lateral surfaces of the fin-type active region; and a gate line extending on the gate dielectric layer to cover the upper surface and opposite lateral surfaces of the fin-type active region and to cross the fin-type active region. The gate line includes an aluminum (Al) doped metal-containing layer extending to cover the upper surface and opposite lateral surfaces of the fin-type active region to a uniform thickness, and a gap-fill metal layer extending on the Al doped metal-containing layer over the fin-type active region. Related fabrication methods are also described.Type: GrantFiled: November 26, 2012Date of Patent: January 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: June-hee Lee, Jae-yeol Song, Hye-Ian Lee, Hong-bae Park, Sang-jin Hyun
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Patent number: 9236313Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.Type: GrantFiled: December 8, 2014Date of Patent: January 12, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Publication number: 20150093888Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.Type: ApplicationFiled: December 8, 2014Publication date: April 2, 2015Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Patent number: 8932922Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.Type: GrantFiled: May 26, 2011Date of Patent: January 13, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Publication number: 20140302652Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities.Type: ApplicationFiled: June 19, 2014Publication date: October 9, 2014Inventors: Hyung-Seok Hong, Sang-Jin Hyun, Hong-Bae Park, Hoon-Joo Na, Hye-Lan Lee
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Patent number: 8786028Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping.Type: GrantFiled: April 12, 2012Date of Patent: July 22, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Seok Hong, Sang-Jin Hyun, Hong-Bae Park, Hoon-Joo Na, Hye-Lan Lee
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Patent number: 8580629Abstract: A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.Type: GrantFiled: September 23, 2011Date of Patent: November 12, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Hong-Bae Park, Sang-Jin Hyun, Hu-Yong Lee, Hoon-Joo Na, Jeong-Hee Han, Hye-Lan Lee, Hyung-Seok Hong
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Publication number: 20130277748Abstract: A semiconductor device includes a fin-type active region; a gate dielectric layer covering an upper surface and opposite lateral surfaces of the fin-type active region; and a gate line extending on the gate dielectric layer to cover the upper surface and opposite lateral surfaces of the fin-type active region and to cross the fin-type active region. The gate line includes an aluminum (Al) doped metal-containing layer extending to cover the upper surface and opposite lateral surfaces of the fin-type active region to a uniform thickness, and a gap-fill metal layer extending on the Al doped metal-containing layer over the fin-type active region. Related fabrication methods are also described.Type: ApplicationFiled: November 26, 2012Publication date: October 24, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: June-Hee LEE, Jae-yeol Song, Hye-Ian Lee, Hong-bae Park, Sang-jin Hyun
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Patent number: 8513740Abstract: A complementary metal oxide semiconductor (CMOS) device including: a semiconductor substrate including a NMOS region and a PMOS region; a NMOS metal gate stack structure on the NMOS region and including a first high dielectric layer, a first barrier metal gate on the first high dielectric layer and including a metal oxide nitride layer, and a first metal gate on the first barrier metal gate; and a PMOS metal gate stack structure on the PMOS region and including a second high dielectric layer, a second barrier metal gate on the second high dielectric layer and including a metal oxide nitride layer, and a second metal gate on the second barrier metal gate.Type: GrantFiled: September 1, 2010Date of Patent: August 20, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-bae Park, Sug-hun Hong, Sang-jin Hyun, Hoon-ju Na, Hye-lan Lee, Hyung-seok Hong
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Patent number: 8367502Abstract: The method involves providing a semiconductor substrate comprising first and second regions in which different conductive metal-oxide semiconductor (MOS) transistors are to be formed. A gate dielectric layer above the semiconductor substrate sequentially forming a first metallic conductive layer and a second metallic conductive layer on and above the gate dielectric layer; covering the second region with a mask, and performing ion plantation of a first material into the first metallic conductive layer of the first region. Removing the second metallic conductive layer of the first region and forming a first gate electrode of the first region and a second gate electrode of the second region by patterning the gate dielectric layer and the first metallic conductive layer of the first region, and the gate dielectric layer, the first metallic conductive layer, and the second metallic conductive layer of the second region.Type: GrantFiled: December 17, 2009Date of Patent: February 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hoon-joo Nah, Hyung-seok Hong
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Publication number: 20120292715Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities.Type: ApplicationFiled: April 12, 2012Publication date: November 22, 2012Inventors: Hyung-Seok HONG, Sang-Jin HYUN, Hong-Bae PARK, Hoon-Joo NA, Hye-Lan LEE
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Publication number: 20120280330Abstract: Semiconductor devices including first and second fin active regions protruding vertically from a substrate and integrally formed with the substrate, a gate insulation layer formed on the first and second fin active regions, a first gate metal contacting the gate insulation layer on the first fin active region, and a second gate metal contacting the first gate metal on the first fin active region and contacting the gate insulation layer on the second fin active region.Type: ApplicationFiled: March 16, 2012Publication date: November 8, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hye-Lan Lee, Hong-Bae Park, Sang-Jin Hyun, Sang-Bom Kang, Jae-Jung Kim
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Patent number: 8293599Abstract: A semiconductor device that has a dual gate having different work functions is simply formed by using a selective nitridation. A gate insulating layer is formed on a semiconductor substrate including a first region and a second region, on which devices having different threshold voltages are to be formed. A diffusion inhibiting material is selectively injected into the gate insulating layer in one of the first region and the second region. A diffusion layer is formed on the gate insulating layer. A work function controlling material is directly diffused from the diffusion layer to the gate insulating layer using a heat treatment, wherein the gate insulting layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region. The gate insulating layer is entirely exposed by removing the diffusion layer. A gate electrode layer is formed on the exposed gate insulating layer.Type: GrantFiled: August 12, 2009Date of Patent: October 23, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Publication number: 20120238067Abstract: Methods of fabricating semiconductor devices including providing a substrate having a channel region defined therein; forming an insulation layer on the substrate; forming a gate trench for forming a gate electrode having a sidewall portion, a bottom portion and an edge portion between the sidewall portion and the bottom portion on the insulation layer, the gate electrode trench overlapping the channel region; and forming a gate electrode in the gate electrode trench. Forming the gate electrode includes forming a first metal layer pattern in the gate electrode trench and forming a second metal layer pattern on the first metal layer pattern.Type: ApplicationFiled: March 16, 2012Publication date: September 20, 2012Inventors: Won-Cheol Jeong, Yun-Young Yeoh, Dong-Won Kim, Hong-Bae Park, Hag-Ju Cho
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Publication number: 20120122309Abstract: A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.Type: ApplicationFiled: September 23, 2011Publication date: May 17, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Hong-Bae PARK, Sang-Jin Hyun, Hu-Yong Lee, Hoon-Joo Na, Jeong-Hee Han, Hye-Lan Lee, Hyung-Seok Hong
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Publication number: 20110223758Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.Type: ApplicationFiled: May 26, 2011Publication date: September 15, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Publication number: 20110180879Abstract: Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.Type: ApplicationFiled: December 20, 2010Publication date: July 28, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hye-Lan Lee, Hong-Bae Park, Sang-Jin Hyun, Yu-Gyun Shin, Sug-Hun Hong, Hoon-Joo Na, Hyung-Seok Hong