Abstract: A method for driving a liquid crystal display, includes receiving source data, reducing the number of bits of the source data, thereby generating a reduced-bit source data, comparing the reduced-bit source data of a previous frame with the reduced-bit source data of a current frame to select a preset modulated data in accordance with the result of the comparison, and modulating the source data by using the selected modulated data.

Abstract: A flat luminescent lamp and a method for manufacturing the same are disclosed in the present invention. More specifically, a flat luminescent lamp includes first and second substrates each having a plurality of grooves in sides which the first and second substrates face into each other, first and second electrodes in the grooves, first and second phosphor layers in the first and second substrates including the first and second electrodes, respectively, and a frame for sealing the first and second substrates.

Abstract: Methods and apparatus for oxygen radical annealing or plasma annealing various layers (e.g., a lower electrode, a dielectric layer, or an upper electrode) of a microelectronic capacitor on a substrate are provided. By oxygen radical or plasma annealing the lower electrode of the capacitor, the leakage current characteristic of the capacitor may be improved such that the leakage current is reduced, for example, by a factor of 100 or more. The amount of impurities on the lower electrode may also be reduced. Oxygen radical or plasma annealing the dielectric layer of the capacitor may improve the leakage current characteristics of the capacitor and may reduce the amount of impurities in the dielectric layer. By ozone annealing the upper electrode, the leakage current characteristic of the capacitor may be improved and the number of oxygen vacancies formed in the dielectric layer may be reduced.

Abstract: A plasma enhanced chemical vapor deposition apparatus and a method of forming a nitride layer using the same, wherein the plasma enhanced CVD apparatus includes a process chamber including an upper chamber with a dome shape, a lower chamber, and an insulator therebetween, a gas distributing ring, a susceptor for supporting a wafer and heating the process chamber, a plasma compensation ring surrounding the susceptor, a vacuum pump and an electric power source connected to the process chamber. The gas distributing ring has a plurality of upwardly inclined nozzles, allowing upward distribution of reactive gases. The method of forming a nitride layer includes forming a protective film on inner walls of a process chamber, the protective film having at least two layers of differeing dielectric constant, and sequentially supplying reactive gases to the process chamber. A nitride layer formed thereby has low hydrogen content, good density and oxidation resistance.

Abstract: A capacitor in which a generation of a bad storage node can be reduced and a method of manufacturing the same. An opening is formed at a portion of an insulating layer on a semiconductor substrate for exposing a conductive structure under the insulating layer. A polysilicon film is formed on a top surface of the insulating layer and a sidewall and a bottom surface of the opening. A supporting film is formed on the polysilicon film. The polysilicon film and the supporting film are partially etched so that the polysilicon film and the supporting film remain only on the sidewall and the bottom surface of the opening, thereby forming a storage electrode. A dielectric film and a plate electrode are formed on the storage electrode. The generation of a bad capacitor can be reduced by using the supporting film to keep the node of the storage electrode from being inclined.

Abstract: A multi-finger type electrostatic discharge protection circuit is disclosed, In an NMOS type ESD protection circuit, a pair of gates are formed in parallel with each other in one of multiple active regions so as to enable all the gate fingers in the active regions to perform npn bipolar operations uniformly. The present invention discharges an ESD pulse effectively by forming one or more additional n+ (or p+) type active regions, which are connected to Vcc (or Vss), between respective active regions.

Abstract: An ESD protection circuit including an NMOS transistor connected between an input/output pad and a ground. The NMOS transistor has a parasitic bipolar transistor, and at least one diode is connected between the input/output pad and the NMOS transistor.

Abstract: A flat luminescent lamp includes first and second substrates attached to each other at a plurality of adhesive portions, a plurality of discharge spaces in regions other than the plurality of adhesive portions between the first and second substrates, first and second electrodes arranged in the discharge spaces to be separated from each other, first and second phosphor layers formed in the discharge spaces, and first and second frames sealing the first and second substrates.

Abstract: A flat luminescent lamp and a method for manufacturing the same are disclosed in the present invention. More specifically, a flat luminescent lamp includes first and second substrates each having a plurality of grooves in sides which the first and second substrates face into each other, first and second electrodes in the grooves, first and second phosphor layers in the first and second substrates including the first and second electrodes, respectively, and a frame for sealing the first and second substrates.

Abstract: An electrostatic discharge protecting circuit for a semiconductor device is provided and includes a first circuit portion including an N-type MOS field effect transistor formed on a P-type silicon substrate and a P-type MOS field effect transistor formed on an N-type well in the P-type silicon substrate. The electrostatic discharge protecting circuit operates in a normal operating mode and an electrostatic discharge evaluation mode. In the normal operating mode, the N- and P-type MOS transistors operate as an output buffer connected to an internal circuit. In the electrostatic discharge characteristic mode, an electrostatic discharge signal is applied from an external source through a pad and switching devices included in a second portion of the electrostatic discharge protecting circuit connect a bulk terminal of the N-type MOS transistor to a ground voltage, thereby improving electrostatic discharge characteristics of the semiconductor device.

Abstract: A ferroelectric random access memory (FRAM) device, and a fabrication method therefor, includes seed layers above and below a ferroelectric layer. The seed layers formed above and below faces of the ferroelectric layer can prevent an imprint phenomenon from being generated in a ferroelectric capacitor by making the characteristics of the upper and lower interfaces of the ferroelectric layer be the same. This is accomplished by providing upper and lower seed layers that are crystallized prior to the ferroelectric layer during a thermal treatment. This results in crystallization occurring from the upper and lower faces to the center of the ferroelectric layer, making the characteristics of the upper and lower interfaces of the ferroelectric layer the same, thereby improving ferroelectric capacitor characteristics.

Abstract: A ferroelectric random access memory (FRAM) device, and a fabrication method therefor, includes seed layers above and below a ferroelectric layer. The seed layers formed above and below faces of the ferroelectric layer can prevent an imprint phenomenon from being generated in a ferroelectric capacitor by making the characteristics of the upper and lower interfaces of the ferroelectric layer be the same. This is accomplished by providing upper and lower seed layers that are crystallized prior to the ferroelectric layer during a thermal treatment. This results in crystallization occurring from the upper and lower faces to the center of the ferroelectric layer, making the characteristics of the upper and lower interfaces of the ferroelectric layer the same, thereby improving ferroelectric capacitor characteristics.

Abstract: The method of fabricating a semiconductor device having a dual-gate provides a semiconductor substrate with a gate insulating film formed on a first portion and a second portion thereof and a polysilicon layer formed on the gate insulating film. A first dopant of a first conductive type is implanted in the polysilicon layer covering the first portion, and a second dopant of a second conductive type is implanted in the polysilicon layer covering the second portion. Then, the polysilicon layer covering the first portion is selectively etched using a first mask to form a first gate, and a third dopant of the first conductive type is implanted to form source/drain LDD regions on both sides of the first gate. Thereafter, the polysilicon layer covering the second portion is selectively etched using a second mask to form a second gate, and a fourth dopant of the second conductive type is implanted to form source/drain LDD regions on both sides of the second gate.

Abstract: A method for forming a capacitor of a semiconductor device. A lower electrode is prebaked before a dielectric layer is formed on the lower electrode. As a result, moisture or contaminants are removed from the lower electrode, increasing adhesion between the lower electrode and the dielectric layer formed on the lower electrode, thereby preventing the dielectric layer from being lifted and cracked due to inferior coating properties.