Patents by Inventor Hong-Da Chang

Hong-Da Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220285295
    Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Wei-Han CHIANG, Ming-Da CHENG, Ching-Ho CHENG, Wei Sen CHANG, Hong-Seng SHUE, Ching-Wen HSIAO, Chun-Hung CHEN
  • Publication number: 20220278013
    Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Chun-Chang Ting, Chi-Jen Chen
  • Patent number: 11398413
    Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: July 26, 2022
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Chun-Chang Ting, Chi-Jen Chen
  • Publication number: 20210104465
    Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.
    Type: Application
    Filed: December 17, 2020
    Publication date: April 8, 2021
    Inventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
  • Publication number: 20210074603
    Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.
    Type: Application
    Filed: January 6, 2020
    Publication date: March 11, 2021
    Inventors: Hong-Da Chang, Chun-Chang Ting, Chi-Jen Chen
  • Patent number: 10903167
    Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 26, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
  • Publication number: 20200350285
    Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.
    Type: Application
    Filed: August 29, 2019
    Publication date: November 5, 2020
    Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
  • Publication number: 20200203277
    Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 25, 2020
    Inventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
  • Publication number: 20200043908
    Abstract: A package stacked structure and a method for fabricating the same are provided. The method includes providing a wiring structure disposed with a carrier and a carrier structure provided with an electronic component. The wiring structure is bonded to the carrier structure via a plurality of conductive elements. An encapsulating layer is formed between the wiring structure and the carrier structure and encapsulates the conductive elements and the electronic component. The carrier is then removed. With the arrangement of the carrier, the structural strength of the wiring structure is improved, and warpage of the wiring structure is prevented before stacking the wiring structure onto the carrier structure.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 6, 2020
    Inventors: Chee-Key Chung, Chang-Fu Lin, Han-Hung Chen, Jen-Chieh Hsiao, Rung-Jeng Lin, Kuo-Hua Yu, Hong-Da Chang
  • Publication number: 20190214372
    Abstract: An electronic package is provided, including: a first circuit structure; an electronic component and a conductive pillar disposed on the first circuit structure; an encapsulation layer encapsulating the electronic component and the conductive pillar; a second circuit structure disposed on the encapsulation layer; and a shielding layer encapsulating the first circuit structure, a side surface of the encapsulation layer, and a side surface of the second circuit structure. The electronic component is surrounded by the shielding layer, and is protected from electromagnetic interference. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: March 18, 2019
    Publication date: July 11, 2019
    Inventors: Hong-Da Chang, Yih-Jenn Jiang
  • Publication number: 20180068983
    Abstract: An electronic package is provided, including: a first circuit structure; an electronic component and a conductive pillar disposed on the first circuit structure; an encapsulation layer encapsulating the electronic component and the conductive pillar; a second circuit structure disposed on the encapsulation layer; and a shielding layer encapsulating the first circuit structure, a side surface of the encapsulation layer, and a side surface of the second circuit structure. The electronic component is surrounded by the shielding layer, and is protected from electromagnetic interference. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: April 24, 2017
    Publication date: March 8, 2018
    Inventors: Hong-Da Chang, Yih-Jenn Jiang
  • Patent number: 9659806
    Abstract: A semiconductor package and a method for fabricating the semiconductor package are provided. The semiconductor package includes a base layer, a plurality of conductive pillars, a semiconductor element, and an encapsulation. The base layer has opposing first and second surfaces and a receiving part. The conductive pillars are formed on the second surface. Each of the conductive pillars has first and second terminals, and the second terminal is distant from the second surface of the base layer. The semiconductor element is received in the receiving part, and has opposing active and passive surfaces, and the active surface is exposed from the first surface. The encapsulation is formed on the second surface, encapsulates the conductive pillars and the semiconductor element, and has opposing third and fourth surfaces, and the second terminals of the conductive pillars are exposed from the fourth surface. The semiconductor package is provided with the conductive pillars having fine pitches.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: May 23, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Shih-Kuang Chiu
  • Patent number: 9607974
    Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: March 28, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-Tang Lin, Shih-Ching Chen, Yi-Che Lai, Hong-Da Chang, Hung-Wen Liu, Yi-Wei Liu, Hsi-Chang Hsu
  • Patent number: 9520304
    Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: December 13, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Yi-Che Lai, Chi-Hsin Chiu, Shih-Kuang Chiu
  • Patent number: 9502335
    Abstract: A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: November 22, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chieh-Lung Lai, Hsien-Wen Chen, Hong-Da Chang, Mao-Hua Yeh
  • Patent number: 9487393
    Abstract: A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: November 8, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Hsin-Yi Liao, Chun-An Huang, Shih-Kuang Chiu, Chien-An Chen
  • Patent number: 9425119
    Abstract: A package structure is provided, which includes: a wafer having a surface with a groove, a thin film closing an open end of the groove and electrical contacts; a chip having a surface with a conductive layer and an opposite surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the wafer with the seal ring surrounding the thin film and the electrical contacts located outside the seal ring; an encapsulant formed on the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant with one ends exposed from a top surface of the encapsulant and the other ends in electrical connection with the electrical contacts; and a through hole penetrating the wafer and communicating with the concave portion, thereby reducing the fabrication cost and size of the package structure.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: August 23, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Shih-Kuang Chiu
  • Publication number: 20160141227
    Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 19, 2016
    Inventors: Chun-Tang Lin, Shih-Ching Chen, Yi-Che Lai, Hong-Da Chang, Hung-Wen Liu, Yi-Wei Liu, Hsi-Chang Hsu
  • Publication number: 20160071784
    Abstract: A semiconductor package and a method for fabricating the semiconductor package are provided. The semiconductor package includes a base layer, a plurality of conductive pillars, a semiconductor element, and an encapsulation. The base layer has opposing first and second surfaces and a receiving part. The conductive pillars are formed on the second surface. Each of the conductive pillars has first and second terminals, and the second terminal is distant from the second surface of the base layer. The semiconductor element is received in the receiving part, and has opposing active and passive surfaces, and the active surface is exposed from the first surface. The encapsulation is formed on the second surface, encapsulates the conductive pillars and the semiconductor element, and has opposing third and fourth surfaces, and the second terminals of the conductive pillars are exposed from the fourth surface. The semiconductor package is provided with the conductive pillars having fine pitches.
    Type: Application
    Filed: July 28, 2015
    Publication date: March 10, 2016
    Inventors: Hong-Da Chang, Shih-Kuang Chiu
  • Publication number: 20150344299
    Abstract: A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path.
    Type: Application
    Filed: August 7, 2015
    Publication date: December 3, 2015
    Inventors: Hong-Da Chang, Hsin-Yi Liao, Chun-An Huang, Shih-Kuang Chiu, Chien-An Chen