Abstract: Disclosed are compounds of formula (I) Where Ar1, X, R3, R4, R5 and R6 are defined herein. The compounds of the invention inhibit production of cytokines involved in inflammatory processes and are thus useful for treating diseases and pathological conditions involving inflammation such as chronic inflammatory disease. Also disclosed are processes for preparing these compounds and pharmaceutical compositions comprising these compounds.

Abstract: Disclosed are compounds of formula (I) Where Ar1, X, Y, Q, W, R3, R4, R5, R6 and Ry are defined herein. The compounds of the invention inhibit production of cytokines involved in inflammatory processes and are thus useful for treating diseases and pathological conditions involving inflammation such as chronic inflammatory disease. The compounds are also useful for treating diseases or conditions related to oncology and anticoagulant or fibrinolytic therapy. Also disclosed are processes for preparing these compounds and pharmaceutical compositions comprising these compounds.

Abstract: Disclosed are compounds of formula (I) Where Ar1, X, Y, Q, W, R3, R4, R5, R6 and Ry are defined herein. The compounds of the invention inhibit production of cytokines involved in inflammatory processes and are thus useful for treating diseases and pathological conditions involving inflammation such as chronic inflammatory disease. The compounds are also useful for treating diseases or conditions related to oncology and anticoagulant or fibrinolytic therapy. Also disclosed are processes for preparing these compounds and pharmaceutical compositions comprising these compounds.

Abstract: The method and circuit of the present invention compensates a timing change over PVT variations without adverse impact on the system. The method and circuit uses two digital programmable delay circuits which have a Master/Slave relationship. The master programmable delay circuit tracks a delay over PVT and readjusts the delay whenever there is a need for calibration due to PVT variations. The slave programmable delay circuit compensates the timing change by delaying the real clock signal when the master programmable delay circuit completes the delay locking process. The resulting circuit is small, flexible, PVT calibrated, and consumes very little power. It can be used with any reference clock to support various timing requirements at different frequencies.

Abstract: The invention provides a system and method for providing scalability in an integrated circuit (IC) having a package coupled to a die through package balls. The die includes a plurality of input/output (I/O) slots and a hardmac configured to implement a logic function. A patch board is included between the hardmac and the I/O slots, wherein the hardmac includes a plurality of attachment points. The hardmac is attached to the plurality of I/O slots through the patch board, wherein adjacent attachment points join to non-adjacent I/O slots through the patch board.

Abstract: Disclosed compounds of formula (I) which inhibit production of cytokines involved in inflammatory processes and are thus useful for treating diseases and pathological conditions involving inflammation such as chronic inflammatory disease. Also disclosed are processes for preparing these compounds and pharmaceutical compositions comprising these compounds.

Abstract: The invention provides a system and method for providing scalability in an integrated circuit (IC) having a package coupled to a die through package balls. The die includes a plurality of input/output (I/O) slots and a hardmac configured to implement a logic function. A patch board is included between the hardmac and the I/O slots, wherein the hardmac includes a plurality of attachment points. The hardmac is attached to the plurality of I/O slots through the patch board, wherein adjacent attachment points join to non-adjacent I/O slots through the patch board.

Abstract: The method and circuit of the present invention compensates a timing change over PVT variations without adverse impact on the system. The method and circuit uses two digital programmable delay circuits which have a Master/Slave relationship. The master programmable delay circuit tracks a delay over PVT and readjusts the delay whenever there is a need for calibration due to PVT variations. The slave programmable delay circuit compensates the timing change by delaying the real clock signal when the master programmable delay circuit completes the delay locking process. The resulting circuit is small, flexible, PVT calibrated, and consumes very little power. It can be used with any reference clock to support various timing requirements at different frequencies.

Abstract: The digitally programmable delay circuit to correct timing skew between data and clock is developed. The digitally programmable delay circuit may be built by cascading delay cells. The delay circuit uses delay cells comprising simple digital elements such as inverters and tri-state inverters to eliminate the intrinsic delay and achieves linearity and monotinicity. The delay cell may be used as a building module which is repeatedly used in a serial fashion. The delay range is fully programmable from the delay of one delay cell to infinity if the chip area is available. The delay range can be scaled by adding more delay cells.

Abstract: Disclosed are compounds of formula (I): wherein R1 and R2 are defined herein, which are useful as inhibitors of the kinase activity of the I?B kinase (IKK) complex. The compounds are therefore useful in the treatment of IKK mediated diseases including autoimmune diseases inflammatory diseases and cancer. Also disclosed are pharmaceutical compositions comprising these compounds and processes for preparing these compounds.

Abstract: Disclosed are compounds of formula (I): wherein R1 and R2 are defined herein, which are useful as inhibitors of the kinase activity of the I?B kinase (IKK) complex. The compounds are therefore useful in the treatment of IKK mediated diseases including autoimmune diseases inflammatory diseases and cancer. Also disclosed are pharmaceutical compositions comprising these compounds and processes for preparing these compounds.

Abstract: Disclosed are compounds of formula (I) The compounds inhibit production of cytokines involved in inflammatory processes and are thus useful for treating diseases and pathological conditions involving inflammation such as chronic inflammatory disease. Also disclosed are processes for preparing these compounds and the pharmaceutical compositions comprising these compounds.

Abstract: Disclosed are compounds of formula (I): wherein R1 and R2 are defined herein, which are useful as inhibitors of the kinase activity of the I?B kinase (IKK) complex. The compounds are therefore useful in the treatment of IKK mediated diseases including autoimmune diseases inflammatory diseases and cancer. Also disclosed are pharmaceutical compositions comprising these compounds and processes for preparing these compounds.

Abstract: Disclosed are compounds of formula (I) which inhibit production of cytokines involved in inflammatory processes and are thus useful for treating diseases and pathological conditions involving inflammation such as chronic inflammatory disease. Also disclosed are processes for preparing these compounds and pharmaceutical compositions comprising these compounds.

Abstract: The present invention is a method and apparatus for implementing a source synchronous interface in a platform using a Generic Source Synchronous Interface (GSSI) infrastructure. The GSSI infrastructure includes the GSSI bit slices and clock management system. The GSSI bit slice includes balanced cells and bit delay elements, and may be placed either within or close to IO buffers. The GSSI clock management system includes strategically placed frame delay elements with automatic on-chip calibration and control to satisfy various clock-data phase relationships. The GSSI methodology shows how different SSIs may be constructed by combining the common GSSI architecture with unique metal layer configurations. The GSSI architecture solves a critical challenge for platform-based design such as RapidChip™ and the like. The GSSI approach introduces a completely new way to implement various SSIs based on a common minimally diffused GSSI bit slice and clock management infrastructure.

Abstract: The digital programmable delay scheme with automatic calibration is an alternative to PLLs, DLLs, fixed delay cells and other methods of delay. The method and circuit sets a delay in a programmable delay cell in an oscillator circuit and uses a reference clock to calibrate the oscillator clock frequency. The programmable delay, once set, may then be used to determine a desired delay for a signal that passes through the programmable delay cell as well as another portion of the oscillator circuit. The circuit preferably uses two counters that are controlled by calibration and control logic in which one counter is clocked by the reference clock and the other is clocked by the oscillator circuit clock. After a predetermined time, the calibration and control logic compares the two count values and determines if the programmable delay cell of the oscillator circuit needs to be adjusted.

Abstract: The digital programmable delay scheme with automatic calibration is an alternative to PLLs, DLLs, fixed delay cells and other methods of delay. The method and circuit sets a delay in a programmable delay cell in an oscillator circuit and uses a reference clock to calibrate the oscillator clock frequency. The programmable delay, once set, may then be used to determine a desired delay for a signal that passes through the programmable delay cell as well as another portion of the oscillator circuit. The circuit preferably uses two counters that are controlled by calibration and control logic in which one counter is clocked by the reference clock and the other is clocked by the oscillator circuit clock. After a predetermined time, the calibration and control logic compares the two count values and determines if the programmable delay cell of the oscillator circuit needs to be adjusted.

Abstract: Disclosed are compounds of formula (I) 1

Abstract: Disclosed are compounds of formula (I): 1

Abstract: A built-in self test implementation for testing the speed and timing margins of the IO pins of a source synchronous IO interface (SSIO). The implementation preferably includes built-in self test logic including a pseudo-random pattern generator which is configured to generate input sequences. Buffers are connected to the IO pins, and the buffers are configured to receive the input sequences. The buffers are connected to multiple input signature registers, and the multiple input signature registers are configured to receive the input sequences from the pseudo-random pattern generator and generate signatures. Comparators are provided to compare the signatures to expected vector values and generate a pass/fail output signal. Preferably, at least one programmable delay cell is disposed between each buffer and the multiple input signature registers. The programmable delay cells provide that propagation delays can be set to perform timing margin tests.