Abstract: Compounds for use in treating or preventing human immunodeficiency virus (HIV) infection are disclosed. The compounds have the following Formula (I): including stereoisomers and pharmaceutically acceptable salts thereof. Methods associated with the preparation and use of the disclosed compounds, as well as pharmaceutical compositions comprising such compounds are also disclosed.

Abstract: Embodiments of the present disclosure provide a protective device for a submarine pipeline, comprising an internal pipeline, a protective casing, and a support explosion-proof assembly; wherein the protective casing is disposed outside the internal pipeline, and a cavity body is disposed between the protective casing and the internal pipeline; the support explosion-proof assembly is disposed in the cavity body; the support explosion-proof assembly includes a plurality of support columns, the support columns are disposed in the cavity body, and one end of the support columns away from the protective casing supported on the internal pipeline, the plurality of the support columns disposed at intervals in a circumferential direction along the internal pipeline, and an explosion-proof baffle with elastic deformation capability is disposed between two adjacent support columns.

Abstract: A directional polymerisation fluorescent probe PCR and a test kit, wherein directional primer pair 5? end complementary binding, sensitising, fluorescent probe 3? end directional polymerisation and melting PCR are performed on the basis of primers and probe specific sequences, primer design uses pair side original primer 5? end 5-10 bp reverse base sequences, added to primer pair front ends according to the 5?-3? direction to form a “5? reverse complementary sequence” chimeric primer pair for directional polymerisation, and 5? complementarity enables amplification product 3? ends to also be mutual templates and mutual primers for amplification. Sensitivity is increased by >2n geometric progression amplification, and competition decreases primer 3? polymerisation PD non-specificity.

Abstract: The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.

Abstract: A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first potion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.

Abstract: A contactor includes: a terminal group including a first terminal and a second terminal; a conductive strip including a first conduction section and a second conduction section that are movably connected, where the first conduction section is connected to the first terminal; a microswitch connected to the second conduction section, where at least two microswitches, at least two conductive strips, and at least two terminal groups are arranged and in a one-to-one correspondence; and a driving component configured to drive the at least two microswitches to rotate for driving to implement selective disconnection or connection between corresponding second conduction sections and second terminals. The present disclosure also discloses a charging and distribution system, a vehicle, and a charging pile. The contactor can implement synchronous on-off of multiple high-voltage circuits, and reduce the number of parts of the driving component.

Abstract: Data multicast in compute core clusters is described. An example of an apparatus includes one or more processors including at least a first processor, the first processor including one or more clusters of cores and a memory, wherein each cluster of cores includes multiple cores, each core including one or more processing resources, shared memory, and broadcast circuitry; and wherein a first core in a first cluster of cores is to request a data element, determine whether any additional cores in the first cluster require the data element, and, upon determining that one or more additional cores in the first cluster require the data element, broadcast the data element to the one or more additional cores via interconnects between the broadcast circuitry of the cores of the first core cluster.

Abstract: Locally biased cache replacement for a clustered cache architecture is described. An example of an apparatus includes clusters of cores; a clustered cache including multiple cache partitions for the clusters of cores, each cache partition including multiple cachelines; and a computer memory including memory partitions, each of the cache partitions being associated with a respective local memory partition, wherein each cacheline of the cache partitions includes a cacheline tag, each cacheline tag including a local tag to indicate whether data stored in the cacheline is local data stored in the local memory partition or remote data stored in a remote memory partition, and a used tag to indicate whether data stored in the cacheline is recently accessed; and wherein the clustered cache includes circuitry to select cachelines for cache replacement in a cache partition based on values of the tags of the cachelines.

Abstract: A scalable and configurable clustered systolic array is described. An example of apparatus includes a cluster including multiple cores; and a cache memory coupled with the cluster, wherein each core includes multiple processing resources, a memory coupled with the plurality of processing resources, a systolic array coupled with the memory, and one or more interconnects with one or more other cores of the plurality of cores; and wherein the systolic arrays of the cores are configurable by the apparatus to form a logically combined systolic array for processing of an operation by a cooperative group of threads running on one or more of the plurality of cores in the cluster.

Abstract: Synchronization for data multicast in compute core clusters is described. An example of an apparatus includes one or more processors including at least a graphics processing unit (GPU), the GPU including one or more clusters of cores and a memory, wherein each cluster of cores includes a plurality of cores, each core including one or more processing resources, shared local memory, and gateway circuitry, wherein the GPU is to initiate broadcast of a data element from a producer core to one or more consumer cores, and synchronize the broadcast of the data element utilizing the gateway circuitry of the producer core and the one or more consumer cores, and wherein synchronizing the broadcast of the data element includes establishing a multi-core barrier for broadcast of the data element.

Abstract: A low warping tempered microcrystalline glass, a preparation method therefor and application thereof are provided. The microcrystalline glass has a compressive stress layer extending from surface to interior of the glass, compressive stress at surface of the glass being CS<550 MPa, and the compressive stress layer having the following stress distribution: (a) when depth of the stress layer is 0 ?m?Dol<30 ?m, a stress distribution curve is approximately linear, and absolute value of slope k1 of the stress curve between any two points that are 20 ?m apart on the curve satisfies 2.45<|k1|<5.05; (b) when depth of the stress layer is 30 ?m?Dol?Dol_zero, the stress distribution curve is approximately linear, and absolute value of slope k2 of the stress curve between any two points that are 20 ?m apart on the curve satisfies 1?|k2|?1.5.

Abstract: A method of forming a semiconductor structure includes forming a first conductive contact in a first dielectric layer coupled to a first device and forming a second conductive contact in the first dielectric layer coupled to a second device. A first trench is formed in the first dielectric layer having a first depth and exposing at least a portion of the first conductive contact. A second trench is formed in the first dielectric layer having a second depth different than the first depth and exposing at least a portion of the second conductive contact. A first conductive layer is formed in the first trench and the second trench. A second dielectric layer is formed in the first trench and the second trench over the first conductive layer.

Abstract: The present disclosure discloses a recombinant varicella-zoster virus (VZV) vaccine, including a fusion protein formed by an amino acid sequence of an extracellular domain of a recombinant glycoprotein gE of a live attenuated VZV strain (OKA strain) gene and an Fc fragment of human immunoglobulin. The present disclosure further provides preparation and use of the fusion protein, a corresponding recombinant gene, a eukaryotic expression vector, etc. The fusion protein of the present disclosure has prominent immunogenicity and can induce the high-level expression of neutralizing antibodies in serum.

Abstract: A resistive random access memory (RRAM) device is provided. The RRAM includes: a bottom electrode via disposed in a first dielectric layer; a bottom electrode electrically connected to the bottom electrode via and protruding upwardly from the bottom electrode via in a vertical direction, wherein the bottom electrode has a tapered shape and includes a base portion extending upwardly from a bottom surface to an interface and a tip portion extending upwardly from the interface to a top surface; a top electrode disposed in a second dielectric layer, the top electrode distanced above and vertically aligned with the bottom electrode; and a switching layer disposed between the first dielectric layer and the second dielectric layer, the switching layer enclosing the bottom electrode, wherein a conductive path between the bottom electrode and the top electrode is formed when a forming voltage is applied.

Abstract: A bearing cage assembly comprises multi-group rollers (2), each group has multiple rollers, and each roller is a barrel roller, multiple rollers are stacked together to form a group of rollers, and the end surfaces of each two adjacent rollers contact with each other. Multiple groups of pockets (11) are formed in the cage, and each group of pockets has multiple pockets. The pockets in any group are distributed along the circumference direction of the said cage, and a group of rollers is disposed in each pocket. Multi-group rollers can roll in circumferential direction of the cage. During the rolling process, a great number of contact points are distributed on the raceways, thus the load capacity of the bearing is improved, the friction resistance is low, suitable for the fields where high speed operation is necessary. A planar thrust bearing, a radial bearing and a conical radial-thrust bearing are provided.

Abstract: Examples described herein relate to a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.

Abstract: An apparatus to facilitate hardware enhancements for double precision systolic support is disclosed. The apparatus includes matrix acceleration hardware having double-precision (DP) matrix multiplication circuitry including a multiplier circuits to multiply pairs of input source operands in a DP floating-point format; adders to receive multiplier outputs from the multiplier circuits and accumulate the multiplier outputs in a high precision intermediate format; an accumulator circuit to accumulate adder outputs from the adders with at least one of a third global source operand on a first pass of the DP matrix multiplication circuitry or an intermediate result from the first pass on a second pass of the DP matrix multiplication circuitry, wherein the accumulator circuit to generate an accumulator output in the high precision intermediate format; and a down conversion and rounding circuit to down convert and round an output of the second pass as final result in the DP floating-point format.

Abstract: A bearing cage assembly comprises multi-group rollers (2), each group has multiple rollers, and each roller is a barrel roller, multiple rollers are stacked together to form a group of rollers, and the end surfaces of each two adjacent rollers contact with each other. Multiple groups of pockets (11) are formed in the cage, and each group of pockets has multiple pockets. The pockets in any group are distributed along the circumference direction of the said cage, and a group of rollers is disposed in each pocket. Multi-group rollers can roll in circumferential direction of the cage. During the rolling process, a great number of contact points are distributed on the raceways, thus the load capacity of the bearing is improved, the friction resistance is low, suitable for the fields where high speed operation is necessary. A planar thrust bearing, a radial bearing and a conical radial-thrust bearing are provided.

Abstract: The present invention provides a composition comprising dendritic cells loaded with hHsp60sp, which dendritic cells are from a subject and have been fixed with paraformaldehyde (PFA). The subject may suffer from an autoimmune disease. Also provided are a method for preparing the composition; recombinant human cells comprising a heterologous gene encoding a fusion protein of HLA-E and hHsp60sp or B7sp, and expressing the fusion protein on the surface of the cells; a method for determining a percentage of maximum inhibition of testing the function of the HLA-E restricted CD8+ Treg cells from a subject, determining whether HLA-E restricted CD8+ Treg cells freshly isolated from a subject are defective, or determining whether defective HLA-E restricted CD8+ Treg cells from a subject are correctable; and a method for correcting defective HLA-E restricted CD8+ Treg cells, treating type 1 diabetes (T1D), or treating multiple sclerosis (MS).