Abstract: A capacitance detection method and circuit are provided. The detection method includes: performing charging, base capacitance offsetting, and charge transferring successively on a capacitor to be detected in an i-th first offsetting process of the first offsetting processes, to generate a first output voltage, wherein i?N; performing discharging, base capacitance offsetting, and charge transferring on the capacitor to be detected successively in a j-th second offsetting process of the second offsetting processes, to generate a second output voltage, wherein j?M; and determining a capacitance variation of the capacitor to be detected before and after the capacitor to be detected is affected by an external electric field based on the first output voltages corresponding to N first offsetting processes and the second output voltages corresponding to M second offsetting processes in the detection period.

Abstract: A data processing method, device and multi-sensor fusion method for multi-sensor fusion, which can group data captured by different sensors in different probe dimensions to simultaneous interpreting deep learning data based on pixel elements in the multi-dimensional matrix structure, thereby realize the more effective data mining and feature extraction to support more effective ability of environment perception and target detection.

Abstract: A method includes estimating a first pressure at a first location of a clutch based on a flow rate of a fluid in the clutch, computing a first torque lead value based on the first pressure, computing a second torque lead value based on a second pressure, computing a third torque lead value by combining the first torque lead value and the second torque lead value, and applying torque from a motor of the vehicle based on the third torque lead value.

Abstract: An apparatus to facilitate facilitating forward progress guarantee using single-level synchronization at individual thread granularity is disclosed. The apparatus includes a processor comprising a barrier synchronization hardware circuitry to assign a set of global named barrier identifiers (IDs) to individual execution threads of a plurality of execution threads and synchronize execution of the individual execution threads on a single level via the set of global named barrier IDs; and a plurality of processing resources to execute the plurality of execution threads and comprising divergent barrier scheduling hardware circuitry to facilitate execution flow switching from a first divergent branch executed by a first thread to a second divergent branch executed by a second thread, the execution flow switching performed responsive to the first thread stalling to wait on a named barrier of the set of global named barrier IDs.

Abstract: Disclosed is a noise detection circuit comprising: a control module configured to control a drive module such that a to-be-detected capacitor is charged with a first voltage in a first period, and the control module controls a cancellation module such that a cancellation capacitor is charged with the first voltage in the first period, or such that both terminals of the cancellation capacitor are connected to the first voltage; the control module controls the cancellation module such that a first terminal of the to-be-detected capacitor is connected to a first terminal of the cancellation capacitor in a second period; the control module controls a charge transfer module such that charges of the to-be-detected capacitor and charges of the cancellation capacitor are converted in a third period to generate an output voltage; and a processing module configured to determine a noise value at least based on the output voltage.

Abstract: A hybrid vehicle includes an electric motor and a combustion engine. A K0 clutch couples the combustion engine to a drivetrain of the vehicle. A control module of the vehicle calculates a torque to be applied by the motor to the K0 clutch when initiating engagement of the combustion engine to the drivetrain. The control module calculates two separate torque lead values by two separate methods and calculates the torque by combining the two torque lead values.

Abstract: A RRAM device is provided. The RRAM device includes: a bottom electrode in a first dielectric layer; a switching layer in a second dielectric layer over the first dielectric layer, wherein a conductive path is formed in the switching layer when a forming voltage is applied; and a needle-like-shaped top electrode region in a third dielectric layer over the second dielectric layer. The needle-like-shaped top electrode region includes: an oxygen-rich dielectric layer, wherein a lower end of the oxygen-rich dielectric layer is a tip; and a top electrode over the oxygen-rich dielectric layer.

Abstract: An apparatus for performing chemical mechanical polish on a wafer includes a polishing head that includes a retaining ring. The polishing head is configured to hold the wafer in the retaining ring. The retaining ring includes a first ring having a first hardness, and a second ring encircled by the first ring, wherein the second ring has a second hardness smaller than the first hardness.

Abstract: A vehicle includes an engine, an accelerator pedal, and a controller. The controller is programmed to command torque to the engine based on a set speed of adaptive cruise control and is programmed to, in response to the adaptive cruise control being active, a measured lateral acceleration of the vehicle exceeding a user-defined lateral acceleration threshold during a road curve, and the accelerator pedal being released, reduce a speed of the vehicle below the set speed until the measured lateral acceleration is less than the lateral acceleration threshold.

Abstract: A system, apparatus, method and computer program product determine the location of a receiver, such as one or more sensors, carried by a device, e.g., a robot. In a method, an audio signal is received in response to a predetermined audio signal provided by at least two audio source devices. For the audio signal that is received from a respective audio source device, the method estimates a first impulse response between the respective audio source device and the receiver. For the first impulse response estimated between each respective audio source device of the at least two audio source devices and the receiver, the method removes one or more reflections from the first impulse response to create direct path information. The method also includes determining a location of the receiver based at least in part upon the direct path information.

Abstract: A vehicle includes a powertrain, an inertial measurement unit configured to measure inertial forces exerted onto the vehicle, and a controller. The controller is programmed to control the torque at the powertrain based on a mapped relationship between the inertial forces and a vehicle velocity, wherein the mapped relationship utilizes at least one mapping parameter. The controller is further programmed to estimate a mass of the vehicle based on the mapping parameter.

Abstract: The present disclosure discloses a driving circuit and a related chip and electronic device. The driving circuit is configured to drive a load and includes: a control unit, configured to generate a first control signal and a second control signal; a first output terminal, coupled to the capacitive touch screen; a mutual capacitive driving circuit, including: a first pull-up unit, configured to selectively pull up the first output terminal coupled to a high voltage level according to the first control signal; a first pull-down unit, configured to selectively couple the first output terminal to a low voltage level according to the second control signal; a first low-pass filter circuit, coupled between the control unit and the first pull-up unit; and a second low-pass filter circuit, coupled between the control unit and the first pull-down unit.

Abstract: A capacitance detection circuit is provided, which includes a capacitance control module, a charge conversion module and a filter module connected with each other. The capacitance control module controls a capacitor to be charged/discharged for multiple times and generates a digital voltage signal according to an amount of received charges. The capacitor releases all stored charges after being charged to a preset voltage during each charge/discharge. In response to the digital voltage signal being at a high level, the charge conversion module outputs negative charges with a preset charge amount to the capacitance control module. The preset charge amount is greater than or equal to an amount of the stored charges when the capacitor is charged to the preset voltage. The filter module obtains a value representing a capacitance of the capacitor according to the digital voltage signal.

Abstract: Interconnect structures and methods of forming interconnect structures are disclosed that provide decreased risk of unwanted via formation through interconnect-level dielectric layers. A method of forming an interconnect structure includes forming first and second dielectric layers over a first metal interconnect feature, where the dielectric layers include localized elevated regions caused by a hillock in the first metal interconnect feature. A planarization process removes the localized elevated region of the second dielectric layer, and third and fourth dielectric layers are formed over the planar upper surface of the second dielectric layer. An etching process through the third and fourth dielectric layers, and into the second dielectric layer, provides a trench having a planar bottom surface.

Abstract: An integrated circuit (IC) device includes a chip having a semiconductor substrate and a thermoelectric module embedded in the semiconductor substrate, where the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, where a bottom portion of thermoelectric module extends through a thickness of the semiconductor substrate, and where the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types.

Abstract: The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.