Abstract: A display device includes a driving controller controlling a data driving circuit and providing a clock signal and a driving voltage in response to an image signal and a control signal received from an external source. The driving controller restores a data enable signal having a display period and a blank period in one frame on the basis of the control signal and sets a voltage level of the driving voltage applied to the gate driving circuit in accordance with a duration of the blank period. During a sequence of frames having a changing frame rate, the driving voltage for each respective frame may be set based on the duration of each respective blank period.

Abstract: A display panel driving control circuit includes a configuration channel configured to determine whether a reversible connector not having designated up and down sides is connected in a first connection state or in a second connection state, and to generate a selection signal based on the determination, and a timing control circuit configured to receive image data in the first connection state and image data in the second connection state based on the selection signal, to process the received image data in the first connection state and the received image data in the second connection state, and to generate a data signal based on the processing.

Abstract: A timing controller resetting circuit including: a resistor connected to an output node from which a reset signal is output and a first voltage source which supplies a first voltage; a capacitor connected to the output node and a second voltage source which supplies a second voltage that is lower than the first voltage; a reference voltage source configured to generate a reference voltage that is lower than the first voltage and higher than the second voltage; a comparator including a first input terminal which receives the first voltage, a second input terminal which receives the reference voltage, and an output terminal which outputs a comparison result signal generated by comparing the first voltage with the reference voltage; and a transistor including a first terminal which is connected to the output node, a second terminal which receives the second voltage, and a gate terminal which receives the comparison result signal.

Abstract: In a method of operating a display device supporting a variable frame mode, frame data are received during a constant active period of a frame period including the active period and a variable blank period, the received frame data are written to a frame memory in the active period, the received frame data are outputted to a data driver in the active period to display an image based on the received frame data, a time of the variable blank period is counted, and, when the time of the variable blank period reaches a predetermined threshold blank time, the frame data stored in the frame memory are outputted to the data driver in the variable blank period to display an image based on the frame data stored in the frame memory.

Abstract: A display panel driving apparatus includes a data driving part, a data driving part and an off voltage controlling part. The data driving part is configured to output a data signal to a data line of a display panel. The gate driving part is configured to output a gate signal to a gate line of the display panel. The off voltage controlling part is configured to receive a first off voltage and a second off voltage applied to the gate driving part to generate the gate signal, measure a leakage current of the gate driving part, and control the first off voltage based on the leakage current. Thus, display quality of a display apparatus including the gate driving part may be improved.

Abstract: A display panel driving apparatus includes a data driving part, a gate driving part and an off voltage controlling part. The data driving part is configured to output a data signal to a data line of a display panel. The gate driving part is configured to output a gate signal to a gate line of the display panel. The off voltage controlling part is configured to receive a first off voltage and a second off voltage applied to the gate driving part to generate the gate signal, measure a leakage current of the gate driving part, and control the first off voltage based on the leakage current. Thus, display quality of a display apparatus including the gate driving part may be enhanced.

Abstract: A display device includes a display panel including: a plurality of pixels; and a signal controller which generates, on a frame-by-frame basis, a display signal based on an input image signal and a control signal from an outside. The signal controller includes a memory which stores a preset image signal, a receiver which receives the control signal, a clock signal modulator which generates an internal clock signal having a first frequency during a blank period, which is determined based on the control signal in a frame period, and a data processor which reads the preset image signal from the memory in response to the internal clock signal for an image processing.

Abstract: A display device includes a driving controller controlling a data driving circuit and providing a clock signal and a driving voltage in response to an image signal and a control signal received from an external source. The driving controller restores a data enable signal having a display period and a blank period in one frame on the basis of the control signal and sets a voltage level of the driving voltage applied to the gate driving circuit in accordance with a duration of the blank period. During a sequence of frames having a changing frame rate, the driving voltage for each respective frame may be set based on the duration of each respective blank period.

Abstract: A display apparatus includes a display panel comprising a plurality of data lines and a plurality of gate lines crossing the plurality of data lines, a frequency detector configured to receive an input synchronization signal with an input frequency which is varying in a preset frequency range and to count clock cycles of an input frame in the input synchronization signal, and a synchronization signal generator configured to generate an output synchronization signal which has an insertion frame corresponding to a frame of maximum frequency within the preset frequency range and inset the insertion frame in a vertical blanking period of the input frame, based on the clock count.

Abstract: A display device includes a signal line disposed on a substrate. A signal input line is disposed on the substrate and connected to a driver. A first insulating layer is disposed on the signal line. A second insulating layer is disposed on the signal input line and the first insulating layer. First contact holes penetrate the first insulating layer and the second insulating layer and expose a portion of the signal line. Second contact holes penetrate the second insulating layer and expose a portion of the signal input line. A connecting member connects the signal line and the signal input line through the first and the second contact holes and is disposed on the second insulating layer. The first and the second contact holes are alternately arranged in the second insulating layer.

Abstract: A display device includes a display panel, and a timing controller which includes a memory unit and an image data conversion unit where when a mode selection signal includes information about a first mode at an (n+1)th frame (n is a positive integer), the memory unit maintains a first frame image data stored before the (n+1)th frame among an image data, when the mode selection signal includes information about a second mode, the memory unit stores second frame image data inputted during the (n+1)th frame among the image data, and the image data conversion unit rearranges pixel data included in the data stored in the memory unit among the first frame image data and the second frame image data, and outputs converted image data.

Abstract: A display apparatus includes a display panel comprising a plurality of data lines and a plurality of gate lines crossing the plurality of data lines, a frequency detector configured to receive an input synchronization signal with an input frequency which is varying in a preset frequency range and to count clock cycles of an input frame in the input synchronization signal, and a synchronization signal generator configured to generate an output synchronization signal which has an insertion frame corresponding to a frame of maximum frequency within the preset frequency range and inset the insertion frame in a vertical blanking period of the input frame, based on the clock count.

Abstract: A display panel driving apparatus includes a data driving part, a data driving part and an off voltage controlling part. The data driving part is configured to output a data signal to a data line of a display panel. The gate driving part is configured to output a gate signal to a gate line of the display panel. The off voltage controlling part is configured to receive a first off voltage and a second off voltage applied to the gate driving part to generate the gate signal, measure a leakage current of the gate driving part, and control the first off voltage based on the leakage current. Thus, display quality of a display apparatus including the gate driving part may be improved.

Abstract: A display device includes a signal line disposed on a substrate. A signal input line is disposed on the substrate and connected to a driver. A first insulating layer is disposed on the signal line. A second insulating layer is disposed on the signal input line and the first insulating layer. First contact holes penetrate the first insulating layer and the second insulating layer and expose a portion of the signal line. Second contact holes penetrate the second insulating layer and expose a portion of the signal input line. A connecting member connects the signal line and the signal input line through the first and the second contact holes and is disposed on the second insulating layer. The first and the second contact holes are alternately arranged in the second insulating layer.

Abstract: A mobile terminal includes a display unit to display a left-eye image and a right-eye image, a barrier panel to generate a parallax barrier region, and a barrier controller to adjust the parallax barrier region. A method for controlling a barrier pattern includes calculating a relative position of a barrier panel with respect to a display unit, adjusting a barrier region generated in the barrier panel according to the calculated relative position, and displaying a left-eye image and a right-eye image via the display unit.

Abstract: A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

Abstract: A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

Abstract: Disclosed is a liquid crystal display (LCD) controller with improved dithering and frame rate control to reduce the physical (hardware) cost and power consumption, and a method thereof. The LCD controller utilizes a mechanism of minimizing a size of a dithering pattern register which stores plural gray levels. A duty cycle value for the respective gray levels is determined by using the same bit number as denominator values of the plural gray levels. The LCD controller includes a dithering pattern register section for storing the plural gray levels, modular register counters for performing counting operation to determine a binary value of most significant bit of the respective gray levels, multiplexers for generating data patterns for the respective gray levels in accordance with an output of the respective modular register counters; and a selection means for selecting and generating a corresponding bit of a data pattern corresponding to pixel data provided on a LCD panel.

Abstract: An exponent unit receives an operand and outputs an exponent of the operand that is equal to the number of consecutive bits of the operand that have the same value as the most significant bit (MSB) of the operand. The exponent unit can obtain an exponent value of an operand having a bit width that is greater than a processing bit width of a leading one detector (or a leading zero detector).

Abstract: A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.