Abstract: A digital signal processing system performs different word-length arithmetic operations (e.g., 24-bit arithmetic and 16-bit arithmetic) using the same hardware. The digital signal processing system includes internal buses, a host processor coupled to the internal buses, a DSP coprocessor coupled to the internal buses for performing a digital signal processing under control of the host processor, and first and second data memories coupled to the internal buses. The DSP coprocessor further includes a random access memory (RAM) pointer for generating addresses to access the first and second data memories, a multiply and accumulate (MAC) unit for performing a multiply and accumulate operation, an arithmetic unit, a shift and exponent unit for shifting operands and for evaluating exponents, and a local decoder for decoding DSP commands from the host processor and controlling the RAM pointer, the arithmetic unit, and the shift and exponent unit.

Abstract: A microprocessor with an efficient and powerful coprocessor interface architecture is provided. The microprocessor has a set of generic coprocessor instructions on its instruction map and interface signals dedicated to the coprocessor interface. Depending on which coprocessor is interfaced to the microprocessor, the generic.coprocessor instructions are renamed to the specific coprocessor commands. When a coprocessor instruction for a specific function is fetched and decoded by the host processor, the appropriate command is issued through the coprocessor interface signals to the coprocessor and the coprocessor performs the required tasks. Hence, the coprocessor interfaced with the host processor need not have its own program. The pipelined operations of the coprocessor are synchronized with pipelined operations of the host processor.

Abstract: Disclosed is a liquid crystal display (LCD) controller with improved dithering and frame rate control to reduce the physical (hardware) cost and power consumption, and a method thereof. The LCD controller utilizes a mechanism of minimizing a size of a dithering pattern register which stores plural gray levels. A duty cycle value for the respective gray levels is determined by using the same bit number as denominator values of the plural gray levels. The LCD controller includes a dithering pattern register section for storing the plural gray levels, modular register counters for performing counting operation to determine a binary value of most significant bit of the respective gray levels, multiplexers for generating data patterns for the respective gray levels in accordance with an output of the respective modular register counters; and a selection means for selecting and generating a corresponding bit of a data pattern corresponding to pixel data provided on a LCD panel.

Abstract: An exponent unit receives an operand and outputs an exponent of the operand that is equal to the number of consecutive bits of the operand that have the same value as the most significant bit (MSB) of the operand. The exponent unit can obtain an exponent value of an operand having a bit width that is greater than a processing bit width of a leading one detector (or a leading zero detector).