Patents by Inventor Hong-Yi Huang
Hong-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090212821Abstract: A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed bit a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal and a second output signal according to the first current and the second current.Type: ApplicationFiled: June 18, 2008Publication date: August 27, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hong-Yi Huang, Chun-Tsai Hung, Yuan-Hua Chu
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Patent number: 7576599Abstract: A voltage generating apparatus including a current source, a first voltage source, a second voltage source, a first differential pair, a second differential pair, a voltage divider and a current mirror is provided. The voltage divider is used for reducing a voltage with a negative temperature coefficient, so as to reduce the amplification ratio of the voltage with a positive temperature coefficient used for compensating the negative temperature coefficient.Type: GrantFiled: May 9, 2008Date of Patent: August 18, 2009Assignee: Industrial Technology Research InstituteInventors: Hong-Yi Huang, Ru-Jie Wang, Yuan-Hua Chu
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Patent number: 7551000Abstract: A differential bidirectional transceiver is provided. The differential bidirectional transceiver includes a first current transmitter, a second current transmitter and a receiver. The first current transmitter and the second current transmitter are coupled to a first interconnection and a second interconnection, respectively. Each of the current transmitters includes two current sources and two switches. The receiver includes an input circuit consisting of four differential pairs, a current summation circuit and a buffer.Type: GrantFiled: May 14, 2007Date of Patent: June 23, 2009Assignee: Industrial Technology Research InstituteInventors: Hong-Yi Huang, Ruei-Iun Pu, Yuan-Hua Chu
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Publication number: 20090146625Abstract: A voltage generating apparatus including a voltage generator and a current splitter is provided. The voltage generator has an output node, and generates a first output voltage from the output node. The first output voltage rises when the temperature rises and the current flowing from the output end of the voltage generator is fixed. And the first output voltage drops when the temperature is fixed and the current flowing from the output node of the voltage generator rises. The current splitter is used for increasing the current flowing through the current splitter when the temperature rises. Therefore, the rise of the first output voltage of the voltage generator will be restrained, and the temperature compensation can be achieved.Type: ApplicationFiled: April 29, 2008Publication date: June 11, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hong-Yi Huang, Ru-Jie Wang, Yuan-Hua Chu
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Publication number: 20090146727Abstract: A voltage generating apparatus including a current source, a first voltage source, a second voltage source, a first differential pair, a second differential pair, a voltage divider and a current mirror is provided. The voltage divider is used for reducing a voltage with a negative temperature coefficient, so as to reduce the amplification ratio of the voltage with a positive temperature coefficient used for compensating the negative temperature coefficient.Type: ApplicationFiled: May 9, 2008Publication date: June 11, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hong-Yi Huang, Ru-Jie Wang, Yuan-Hua Chu
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Publication number: 20090141595Abstract: A time-to-digital converter apparatus including a delay phase-locked loop, a subtracter, a multi-phase detector and a Vernier detector is disclosed. The delay phase-locked loop herein includes digital delay components for producing counting signals. The multi-phase detector includes digital delay components for producing delay outputs according to the counting signals and thereby detecting a pulse input signal. The Vernier detector includes digital delay components for detecting the remainder of the pulse input signal according to the difference between the delay outputs produced by the subtracter.Type: ApplicationFiled: May 2, 2008Publication date: June 4, 2009Applicant: Industrial Technology Research InstituteInventors: Hong-Yi Huang, Yi-Jui Tsai, Yuan-Hua Chu
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Publication number: 20090140782Abstract: A spread spectrum clock generating apparatus is disclosed. The spread spectrum clock generating apparatus includes a phase lock loop module and a spread spectrum module. The phase lock loop module is used for dynamically tuning frequency of an output clock. The spread spectrum module includes a counter, a plurality of delta-sigma counters and a data shifter. These delta-sigma counters accumulate input signals, and enable a first overflow signal while accumulation of a last stage delta-sigma counter is overflowed. The frequency of the output clock can be tuned dynamically according to the first overflow signal, and the spectrum of the output clock can be spread.Type: ApplicationFiled: March 11, 2008Publication date: June 4, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hong-Yi Huang, Li-Wei Huang, Yuan-Hua Chu
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Patent number: 7528640Abstract: A digital pulse-width control apparatus including an input module, a digital delay locked loop, a plurality of programmable delay circuits connected in series, and a pulse-width modulation module is provided. The present invention uses the input module to vary a clock signal to reduce the limitation of a duty cycle of the clock signal to the digital pulse-width control apparatus.Type: GrantFiled: May 15, 2007Date of Patent: May 5, 2009Assignee: Industrial Technology Research InstituteInventors: Hong-Yi Huang, Shiun-Dian Jan, Yuan-Hua Chu
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Patent number: 7525355Abstract: A digital delay locked loop including a plurality of controllable delay circuits connected in series, a phase detecting unit, and a delay control unit is disclosed. As an output end of each of the controllable delay circuits is coupled to the phase detecting unit, the phase detecting unit samples a positive received signal at the transition points of a specific period signal transmitted by each of the controllable delay circuits.Type: GrantFiled: May 15, 2007Date of Patent: April 28, 2009Assignee: Industrial Technology Research InstituteInventors: Hong-Yi Huang, Shiun-Dian Jan, Yuan-Hua Chu
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Patent number: 7522084Abstract: A cycle time to digital converter includes a dual delay lock loop, multi phase sampling detector and VDL sampling detector. The dual delay lock loop generates the first voltage corresponding to the first delay time and the second voltage corresponding to the second delay time. The multi phase sampling detector receives first start signal, first stop signal and first voltage to detect a coarse delay time, generates the first group signals according to the coarse delay time, delays the first stop signal by a common delay time to generate the second stop signal, and delays the first start signal by the coarse delay time and the common delay time to generate the second start signal. The VDL sampling detector receives first voltage, second voltage, second start signal and second stop signal for detecting a fine delay time and generates the second group signals according to the fine delay time.Type: GrantFiled: July 13, 2007Date of Patent: April 21, 2009Assignee: Industrial Technology Research InstituteInventors: Hong-Yi Huang, Sheng-Dar Wu, Yuan-Hua Chu
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Patent number: 7466177Abstract: A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range is provided. A differential programmable charge pump is employed to stabilize the current source by complementary connection. The differential programmable charge pump has a pair of differential charge pumps and a current source module to adjust the ratio of charge to discharge, so as to accelerate the range of the adjustable pulse-width ratio of the output clock and increase the output resolution. Further, a ratioless input control stage is employed to simplify the circuit design and avoid static power consumption. Moreover, the control stage adjusts rising pulse width and dropping pulse width at one period, thereby accelerating the lock speed and the range of the adjustable pulse-width ratio (i.e., duty cycle) of the input clock.Type: GrantFiled: July 24, 2006Date of Patent: December 16, 2008Assignee: Industrial Technology Research InstituteInventors: Hong-Yi Huang, Wei-Ming Chiu, Yuan-Hua Chu
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Patent number: 7446585Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.Type: GrantFiled: April 23, 2007Date of Patent: November 4, 2008Assignee: Industrial Technology Research InstituteInventors: Hong-Yi Huang, Shiun-Dian Jan, Yuan-Hua Chu
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Publication number: 20080143403Abstract: A digital delay locked loop including a plurality of controllable delay circuits connected in series, a phase detecting unit, and a delay control unit is disclosed. As an output end of each of the controllable delay circuits is coupled to the phase detecting unit, the phase detecting unit samples a positive received signal at the transition points of a specific period signal transmitted by each of the controllable delay circuits.Type: ApplicationFiled: May 15, 2007Publication date: June 19, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hong-Yi Huang, Shiun-Dian Jan, Yuan-Hua Chu
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Publication number: 20080143413Abstract: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal, and transmits a positive-phase output signal through a positive-phase output signal line. The variable resistance unit regulates an equivalent resistance between the anti-phase output signal line and the positive-phase output signal line according to M bits in a delay-controlled code. The variable capacitance unit regulates an equivalent capacitance between the anti-phase output signal line and the positive-phase output signal line according to N bits in the delay-controlled code.Type: ApplicationFiled: April 23, 2007Publication date: June 19, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hong-Yi Huang, Shiun-Dian Jan, Yuan-Hua Chu
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Publication number: 20080143402Abstract: A digital pulse-width control apparatus including an input module, a digital delay locked loop, a plurality of programmable delay circuits connected in series, and a pulse-width modulation module is provided. The present invention uses the input module to vary a clock signal to reduce the limitation of a duty cycle of the clock signal to the digital pulse-width control apparatus.Type: ApplicationFiled: May 15, 2007Publication date: June 19, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hong-Yi Huang, Shiun-Dian Jan, Yuan-Hua Chu
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Publication number: 20080116936Abstract: A differential bidirectional transceiver is provided. The differential bidirectional transceiver includes a first current transmitter, a second current transmitter and a receiver. The first current transmitter and the second current transmitter are coupled to a first interconnection and a second interconnection, respectively. Each of the current transmitters includes two current sources and two switches. The receiver includes an input circuit consisting of four differential pairs, a current summation circuit and a buffer.Type: ApplicationFiled: May 14, 2007Publication date: May 22, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hong-Yi Huang, Ruei-Iun Pu, Yuan-Hua Chu
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Publication number: 20080111641Abstract: A digitally controlled oscillator (DCO) includes a pulse generator for generating a pulse signal upon an edge of a trigger signal, and at least one delay circuit coupled to delay the pulse signal generated by the pulse generator. The pulse generator is coupled to receive one of the delayed pulse signal from the at least one delay circuit and an enable signal as the trigger signal. A digitally controlled varactor (DCV) includes a transistor having a gate, a source, a drain, and a substrate, wherein at least one of the gate, the source, the drain, and the substrate is coupled to receive one of two or more voltages, wherein at least one of the two or more voltages is not a power supply voltage or ground.Type: ApplicationFiled: November 13, 2006Publication date: May 15, 2008Inventors: Hong-Yi Huang, Jen-Chieh Liu, Yuan-Hua Chu
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Publication number: 20080111720Abstract: A cycle time to digital converter comprises a dual delay lock loop, multi phase sampling detector and VDL sampling detector. The dual delay lock loop generates the first voltage corresponding to the first delay time and the second voltage corresponding to the second delay time. The multi phase sampling detector receives first start signal, first stop signal and first voltage to detect a coarse delay time, generates the first group signals according to the coarse delay time, delays the first stop signal by a common delay time to generate the second stop signal, and delays the first start signal by the coarse delay time and the common delay time to generate the second start signal. The VDL sampling detector receives first voltage, second voltage, second start signal and second stop signal for detecting a fine delay time and generates the second group signals according to the fine delay time.Type: ApplicationFiled: July 13, 2007Publication date: May 15, 2008Inventors: Hong-Yi Huang, Sheng-Dar Wu, Yuan-Hua Chu
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Patent number: 7342419Abstract: A bidirectional current-mode transceiver is provided for improving transmission rates on a transmission line in a manner of current signal transmission, and for reducing the swing of the voltage signal on the transmission line by using a termination resistor, thus improving operating speed. Therefore, the provided transceiver can be applied to a long transmission line.Type: GrantFiled: May 30, 2006Date of Patent: March 11, 2008Assignee: Industrial Technology Research InstituteInventors: Hong-Yi Huang, Ching-Chieh Wu, Yuan-Hua Chu
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Patent number: 7292079Abstract: A DLL-based programmable clock generator using a threshold-trigger delay element and an edge combiner is proposed. A threshold-trigger delay element with full swing complementary output signals consumes no dc power. It exhibits small delay error resulting reduced out jitter. It also increases the linearity of delay time versus control voltage. The circular edge combiner can multiply the input signal at a lower supply voltage. The rise and fall time of output signal are more symmetrical. It also present the multiplication factor of the clock generator can be easy to choose with the increasing of the number of delay elements.Type: GrantFiled: August 2, 2005Date of Patent: November 6, 2007Assignee: Industrial Technology Research InstituteInventors: Hong-Yi Huang, Jian-Hong Shen, Yuan-Hua Chu