Abstract: A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range is provided. A differential programmable charge pump is employed to stabilize the current source by complementary connection. The differential programmable charge pump has a pair of differential charge pumps and a current source module to adjust the ratio of charge to discharge, so as to accelerate the range of the adjustable pulse-width ratio of the output clock and increase the output resolution. Further, a ratioless input control stage is employed to simplify the circuit design and avoid static power consumption. Moreover, the control stage adjusts rising pulse width and dropping pulse width at one period, thereby accelerating the lock speed and the range of the adjustable pulse-width ratio (i.e., duty cycle) of the input clock.

Abstract: A bidirectional current-mode transceiver is provided for improving transmission rates on a transmission line in a manner of current signal transmission, and for reducing the swing of the voltage signal on the transmission line by using a termination resistor, thus improving operating speed. Therefore, the provided transceiver can be applied to a long transmission line.

Abstract: A DLL-based programmable clock generator using a threshold-trigger delay element and an edge combiner is proposed. A threshold-trigger delay element with full swing complementary output signals consumes no dc power. It exhibits small delay error resulting reduced out jitter. It also increases the linearity of delay time versus control voltage. The circular edge combiner can multiply the input signal at a lower supply voltage. The rise and fall time of output signal are more symmetrical. It also present the multiplication factor of the clock generator can be easy to choose with the increasing of the number of delay elements.

Abstract: The present invention provides one pulsewidth control loop (PWCL) device with complementary signals. The PWCL device includes one control stage circuit, one buffer chain, one complementary circuit, two charge pumps, and one comparator. The control stage circuit is used to receive a clock signal and the control signal of the comparator, and output a signal to the buffer chain. The buffer chain is used to receive the output signal from the control stage circuit and output a signal to the complementary circuit. The complementary circuit is used to receive the output signal from the buffer chain and output two complementary signals. Each of the two charge pumps is used to receive one of the output signals from the complementary circuit and output a signal to be one of the inputs of the comparator. The comparator is used to receive the output signals from each of the two charge pumps. Then, the comparator outputs a signal and feedbacks to be one of the input signals of the control stage circuit.

Abstract: A transmission system structure including a signal receiver and a signal transmitter. The signal transmitter that transmits a differential input signal pair to the transmission line is mainly used for pre-charging the input terminal of the signal receiver to a predetermined voltage level. The differential signal pair is transmitted to the transmission line after pre-charging. The signal receiver includes a positive feedback differential amplifier, a coupling circuit and pre-charging device. The pre-charger can pre-charge the differential input terminal of the positive feedback differential amplifier to the predetermined voltage level. During evaluation, the coupling circuit couples from the input terminal to the differential input terminal. When there is a sufficient voltage difference on the differential input terminals, the positive feedback differential amplifier is turned on to amplify the entered differential input signal and outputs it to the differential output terminal.

Abstract: The present invention provides one dual-modulus prescaler using double edge triggered D-flip-flops. The dual-modulus prescaler comprises one double edge triggered synchronous block, one asynchronous block, and one combination logic block. The double edge triggered synchronous block is used to receive an input signal and a divisor selection signal from the combination logic block, and output a synchronous block output signal to the asynchronous block. The asynchronous block is used to receive the synchronous block output signal and output a plurality of signals to the combination logic block. One of the output signals of the asynchronous block is the output signal of the dual-modulus prescaler. The combination logic block is used to receive all the output signals of the asynchronous block and a modulus selection signal. Then, the combination logic block outputs the divisor selection signal and feeds it back to the double edge triggered synchronous block.

Abstract: The present invention provides one pulsewidth control loop (PWCL) device with complementary signals. The PWCL device includes one control stage circuit, one buffer chain, one complementary circuit, two charge pumps, and one comparator. The control stage circuit is used to receive a clock signal and the control signal of the comparator, and output a signal to the buffer chain. The buffer chain is used to receive the output signal from the control stage circuit and output a signal to the complementary circuit. The complementary circuit is used to receive the output signal from the buffer chain and output two complementary signals. Each of the two charge pumps is used to receive one of the output signals from the complementary circuit and output a signal to be one of the inputs of the comparator. The comparator is used to receive the output signals from each of the two charge pumps. Then, the comparator outputs a signal and feedbacks to be one of the input signals of the control stage circuit.

Abstract: A capacitor-coupling acceleration apparatus is an accelerating circuit capable of being applied to interconnect lines in an integrated circuit in order to reduce delay owing to parasitic resistance and capacitance of the interconnect lines in the integrated circuit. The apparatus can be disposed between the interconnect lines. When a signal transmitted on the interconnect line has a change from a low-level voltage to a high-level voltage, the apparatus detects the voltage level change of the signal and provides a charging loop to charge the interconnect line, thereby accelerating the change from the low-level voltage to the high-level voltage. When a signal on the interconnect line has a change from the high-level voltage to the low-level voltage, the apparatus detects the voltage level change of the signal and provides a discharging loop to discharge the interconnect line, thereby accelerating the change from the high-level voltage to the low-level voltage.

Abstract: A bulk input differential logic circuit. The circuit outputs a large signal high enough to assert a logic High and Low by variations of the threshold voltage controlled by the bulk input signal and amplification of the sense amplifier. A boost circuit is disposed on the bulk input terminal, which may receive multiple bulk input signals. This makes it possible to use fewer circuit elements and smaller circuit area for a complicated logic operation.

Abstract: A bulk input differential logic circuit. The circuit outputs a large signal high enough to assert a logic High and Low by variations of the threshold voltage controlled by the bulk input signal and amplification of the sense amplifier. A boost circuit is disposed on the bulk input terminal, which may receive multiple bulk input signals. This makes it possible to use fewer circuit elements and smaller circuit area for a complicated logic operation.

Abstract: A capacitor-coupling acceleration apparatus is an accelerating circuit capable of being applied to interconnect lines in an integrated circuit in order to reduce delay owing to parasitic resistance and capacitance of the interconnect lines in the integrated circuit. The apparatus can be disposed between the interconnect lines. When a signal transmitted on the interconncect line has a change from a low-level voltage to a high-level voltage, the apparatus detects the voltage level change of the signal and provides a charging loop to charge the interconnect line, thereby accelerating the change from the low-level voltage to the high-level voltage. When a signal on the interconncect line has a change from the high-level voltage to the low-level voltage, the apparatus detects the voltage level change of the signal and provides a discharging loop to discharge the interconnect line, thereby accelerating the change from the high-level voltage to the low-level voltage.

Abstract: A capacitor-coupling differential logic circuit handling the output of a differential circuit using coupling capacitors and sense amplifier. The coupling capacitors can couple a control signal to the corresponding internal terminal, i.e., the output terminal of the differential circuit. During evaluation, the differential circuit generates a voltage difference on the internal signal of the internal terminal according to the input signal and the predetermined logic operation. The sense amplifier is used to amplify and output the voltage difference on the internal; signal at the internal terminal.

Abstract: A charge-redistribution low-swing differential logic circuit combining a differential logic network and a charge-redistribution circuit so as to provide a pair of complementary signals having only a small difference, thereby avoiding a time delay. Further, after a sense amplifier is used to amplify the signals, the resulting signals are outputted to sequential differential logic network, wherein the output swing can be reduced by a threshold voltage Vtn (Vtp) on a transistor. In addition, a pipeline is formed by the series connection structure controlled by a true-single-phase clock or by pseudo-single-phase clock, thereby achieving a designed circuit having high-speed and low power dissipation.

Abstract: A hidden refresh 2P2N pseudo SRAM having an array of memory cells. Each of the memory cells includes a cross-couple latch and two PMOS access transistors. The cross-couple latch are structured with two NMOS transistors which are cross coupled to each other and provided to store a pair of signals. The two NMOS transistors have their sources connected to a negative source voltage, and their drains and gates cross coupled to each other. The two PMOS transistors are controlled by a word line and provided to respectively access the two NMOS transistors of the cross-couple latch and a pair of bit lines. The two PMOS transistors have their sources connected to the pair of bit lines and drains connected to the drains of the two NMOS transistors, respectively.

Abstract: A self row-identified hidden refresh circuit for refreshing a pseudo SRAM comprises a latchable burst array. The latchable burst array is composed of several latchable burst units, equipped respectively with a selector, delay elements and a state recording device. The selector selectively outputs a refresh pulse in accordance with the registered state of the state recording device. The refresh pulse is sequentially delayed by passing through the delay elements to refresh several rows of the pseudo SRAM. The state recording device records a first state before the refresh pulse enters the latchable burst units, a second state after the refresh pulse enters the latchable burst units, and the first state when the refresh pulse leaves the latchable burst units. In certain embodiments, the selector may include a multiplexer and the state recording device may include a SR flip-flop.

Abstract: A pipeline-able asynchronous logic circuit is provided that implements a subfunction of a logic function that is distributed into multiple sequential subfunctions. Each subsequent subfunction is applied to a result of an immediately preceding subfunction of the sequence. The asynchronous logic circuit has an output node and a differential logic circuit connected to the output node via a first path. The differential logic circuit applies a particular subfunction to an inputted signal to produce a result signal. The asynchronous logic circuit also has a sense amplifier that is connected to the output node via a second path which is distinct from the first path. The sense amplifier, in response to being enabled, amplifies the result signal produced by the differential logic circuit. The sense amplifier outputs the amplified result signal onto the output node.

Abstract: A latch circuit has an enable circuit responds to clock pulse levels of a first polarity by outputting an enabling voltage of a second polarity opposite to the first polarity. The latch circuit also has first and second inverters which each have an output, a first biasing input connected to a first polarity voltage, a first input, a second a biasing input receiving the enabling voltage from the enable circuit and a second input. When enabled by the enabling voltage, each inverter drives its respective output to a voltage of the first polarity in response to receiving a signal of the second polarity at its first input. Alternatively, when enabled, each inverter drives its respective output to a voltage of the second polarity in response to receiving a signal of the first polarity at its second input. The first input of the first inverter receives, between the leading and trailing edges of the first polarity clock pulse levels, a signal to be stored.