Patents by Inventor Hongbin Zhu
Hongbin Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170140941Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.Type: ApplicationFiled: January 27, 2017Publication date: May 18, 2017Inventors: Hongbin ZHU, Gordon A. HALLER, Fatma A. SIMSEK-EGE
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Patent number: 9613973Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.Type: GrantFiled: August 20, 2015Date of Patent: April 4, 2017Assignee: Micron Technology, Inc.Inventors: Luan C. Tran, Hongbin Zhu, John D. Hopkins, Yushi Hu
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Patent number: 9595531Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.Type: GrantFiled: July 11, 2014Date of Patent: March 14, 2017Assignee: Intel CorporationInventors: Hongbin Zhu, Gordon A Haller, Fatma A Simsek-Ege
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Publication number: 20160336341Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
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Publication number: 20160284719Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.Type: ApplicationFiled: March 23, 2015Publication date: September 29, 2016Inventors: Hongbin Zhu, Gordon A. Haller, Charles H. Dennison, Anish A. Khandekar, Brett D. Lowe, Lining He, Brian Cleereman
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Patent number: 9431410Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.Type: GrantFiled: November 1, 2013Date of Patent: August 30, 2016Assignee: Micron Technology, Inc.Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
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Publication number: 20160233225Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.Type: ApplicationFiled: February 11, 2015Publication date: August 11, 2016Inventors: Hongbin Zhu, Lijing Gou, Gordon Haller, Luan C. Tran
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Publication number: 20160172373Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.Type: ApplicationFiled: February 21, 2016Publication date: June 16, 2016Inventors: John M. Meldrim, Yushi Hu, Rita J. Klein, John D. Hopkins, Hongbin Zhu, Gordon A. Haller, Luan C. Tran
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Publication number: 20160133640Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.Type: ApplicationFiled: July 11, 2014Publication date: May 12, 2016Inventors: HONGBIN ZHU, GORDON A. HALLER, FATMA A. SIMSEK-EGE
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Publication number: 20160099252Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.Type: ApplicationFiled: August 20, 2015Publication date: April 7, 2016Inventors: Luan C. Tran, Hongbin Zhu, John D. Hopkins, Yushi Hu
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Patent number: 9305844Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.Type: GrantFiled: February 19, 2015Date of Patent: April 5, 2016Assignee: Micron Technology, Inc.Inventors: Hongbin Zhu, Gordon Haller, Paul D. Long
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Patent number: 9287379Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.Type: GrantFiled: May 19, 2014Date of Patent: March 15, 2016Assignee: Micron Technology, Inc.Inventors: John M. Meldrim, Yushi Hu, Rita J. Klein, John D. Hopkins, Hongbin Zhu, Gordon A. Haller, Luan C. Tran
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Publication number: 20150333143Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.Type: ApplicationFiled: May 19, 2014Publication date: November 19, 2015Applicant: Micron Technology, Inc.Inventors: John M. Meldrim, Yushi Hu, Rita J. Klein, John D. Hopkins, Hongbin Zhu, Gordon A. Haller, Luan C. Tran
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Publication number: 20150162246Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.Type: ApplicationFiled: February 19, 2015Publication date: June 11, 2015Inventors: Hongbin Zhu, Gordon Haller, Paul D. Long
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Patent number: 9048194Abstract: Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch.Type: GrantFiled: August 9, 2013Date of Patent: June 2, 2015Assignee: MICRON TECHNOLOGY, INC.Inventor: Hongbin Zhu
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Publication number: 20150123189Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.Type: ApplicationFiled: November 1, 2013Publication date: May 7, 2015Applicant: Micron Technology, Inc.Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
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Patent number: 8963156Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.Type: GrantFiled: February 22, 2013Date of Patent: February 24, 2015Assignee: Micron Technology, Inc.Inventors: Hongbin Zhu, Gordon Haller, Paul D. Long
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Publication number: 20150031142Abstract: The present disclosure discloses a device and a method for measuring gas chemical solvent absorption and desorption reaction heat. The device comprises an outer casing; an metal guard inner shell; a reactor; a pressure sensor; a thermal insulation material between the outer casing and the metal guard inner shell; guard electric heaters provided respectively in an upper portion and a lower portion of an outer periphery of the metal guard inner shell; a glass fiber thermal insulation layer between the inner metal guard shell and the reactor; temperature thermocouples provided in the glass fiber thermal insulation layer; a glass fiber board provided in a lower portion of an outer periphery of the reactor; main electric heaters between the glass fiber board and the reactor; a liquid inlet pipe and a gas discharge pipe; a temperature thermistor, a liquid discharge pipe; a data acquisition board; a computer; and a power supply.Type: ApplicationFiled: July 10, 2014Publication date: January 29, 2015Inventors: Jian Zhang, Qingfang Li, Haili Liu, Shijian Lu, Minghua Shang, Xin Wang, Limin He, Shaowei Huang, Xinjun Zhang, Guangling Sun, Tong Shan, Zenglin Wang, Huizhong Pang, Dongjie Liu, Huijuan Yu, Zhiying Sun, Luning Wu, Hongbin Zhu, Ningning Zhang, Lei Zhang, Yinjun Lu
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Publication number: 20140239303Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.Type: ApplicationFiled: February 22, 2013Publication date: August 28, 2014Applicant: Micron Technology, Inc.Inventors: Hongbin Zhu, Gordon Haller, Paul D. Long
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Publication number: 20140167131Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Inventors: Zhenyu Lu, Hongbin Zhu, Gordon A. Haller, Roger W. Lindsay, Andrew Bicksler, Brian J. Cleereman, Minsoo Lee