Abstract: Disclosed is a method for preparing a high-entropy alloy composites reinforced by diamond particles, belonging to the technical field of metal composites preparation. A vacuum coating preparation equipment equipped with an in-situ heating sample stage is used to perform a treatment of high-entropy alloy metallizing coating on the surface of diamond particles to generate modified diamond particles, where the alloy of the coating includes any four, five or six elements among seven elements of Ti, Zr, Hf, Nb, Ta, W and Mo in an equal atomic proportion. The obtained coating generates carbide film in-situ with the surface layer of diamond particles, while the high-entropy alloy covers the carbide film, ensuring a strong bond with the diamond, and the high-entropy alloy composites reinforced by diamond particles are finally prepared.

Abstract: A display substrate and a manufacturing method therefor, and a display device. The display substrate includes a display region and a non-display region surrounding the display region, the non-display region includes a wire having a corner; and the display substrate further includes at least one electrostatic protection circuit, the electrostatic protection circuit is electrically connected with the wire at the corner, and the electrostatic protection circuit is configured to eliminate static electricity generated at the corner.

Abstract: Provided are compounds represented by general formula (I), which can be used for treating ATR kinase-mediated diseases, such as proliferative diseases, such as cancer. Further provided are a pharmaceutical composition of the compound represented by general formula (I), a use thereof in treating ATR kinase-mediated diseases, and a preparation thereof.

Abstract: Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic oxide particles, such as ceria-coated silica; and dual chemical additives for providing the tunable oxide film removal rates and tunable SiN film removal rates; low oxide trench dishing, and high oxide: SiN selectivity. Dual chemical additives comprise at least one silicone-containing compound comprising at least one of (1) ethylene oxide and propylene oxide (EO-PO) group, and at least one of substituted ethylene diamine group on the same molecule; and (2) at least one non-ionic organic molecule having at least two, preferably at least four hydroxyl functional groups.

Abstract: The invention relates to a method for guaranteeing the reliability of real-time scrambling and message transmission by a train control center system. The method comprises the following steps: S1, starting the system for offline message loading and reading; S2, obtaining message data to be scrambled; S3, sending the message to be scrambled to a scrambling operation board for scrambling; S4, performing inverse decoding processing on an operation board; S5, performing comparison after decoding; and S6, outputting effective message data. Compared with the prior art, the invention has the advantages of being capable of guaranteeing the safety and reliability of message data.

Abstract: Chemical mechanical planarization (CMP) polishing compositions, methods and systems are provided to reduce oxide trench dishing and improve over-polishing window stability. High and tunable silicon oxide removal rates, low silicon nitride removal rates, and tunable SiO2:SiN selectivity are also provided. The compositions use unique chemical additives, such as maltitol, lactitol, maltotritol, ribitol, D-sorbitol, mannitol, dulcitol, iditol, D-(?)-Fructose, sorbitan, sucrose, ribose, Inositol, glucose, D-arabinose, L-arabinose, D-mannose, L-mannose, meso-erythritol, beta-lactose, arabinose, or combinations thereof as oxide trench dishing reducing additives.

Abstract: A display substrate includes: a base substrate having a display region and a peripheral region surrounding the display region; a plurality of sub-pixels in the display region; a plurality of data lines in the display region, electrically coupled to the plurality of sub-pixels respectively, and configured to provide a data signal to the plurality of sub-pixels respectively; a plurality of pads in the peripheral region, wherein at least a portion of the plurality of pads are configured to provide a data signal to the plurality of data lines respectively; at least one test data signal line in the peripheral region; at least one test control signal line in the peripheral region; and a plurality of test units in the peripheral region and on a side of the plurality of pads away from the display region.

Abstract: A display substrate, a method for manufacturing the display substrate and a display device are provided. The display substrate includes an Electric Test (ET) region. At least one testing pad and an insulation structure surrounding the testing pad are arranged in the ET region, and a distance between a surface of the insulation structure distal to a base substrate of the display substrate and the base substrate is not greater than a distance between a surface of the testing pad distal to the base substrate and the base substrate.

Abstract: A display substrate and display apparatus are provided. The display substrate includes: a base substrate, including a display area and a bezel area; a plurality of pixel units located in the display area and arranged in an array along a row direction and a column direction on the base substrate; a plurality of scanning signal lines; a gate driver circuit located in the bezel area; a plurality of load compensation units located in the bezel area, the plurality of load compensation units are located between the gate driver circuit and the plurality of pixel units; and a plurality of scanning signal lead wires located in the bezel area and configured to transmit a scanning signal output by the gate driver circuit to the scanning signal lines, where at least one of the scanning signal lead wires crosses at least one of the load compensation units in the row direction.

Abstract: A display substrate and a display device are provided. The display substrate includes: a base substrate including a display area (AA) and a peripheral area (PA); a plurality of sub-pixels (Pxl); a plurality of pins a plurality of leads located in the peripheral area (PA), wherein the plurality of pins electrically connected to the plurality of sub-pixels (Pxl) through the plurality of leads ; a plurality of extension pads electrically connected to the plurality of pins; and a plurality of spacers configured to electrically insulate the plurality of extension pads from each other , wherein orthographic projections of the plurality of spacers on the base substrate do not overlap orthographic projections of the plurality of extension pads on the base substrate .

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes: a base; multiple pixel units arranged in multiple rows along a first direction and multiple columns along a second direction and arranged on the base, and each pixel unit includes multiple sub-pixels, each sub-pixel includes a pixel circuit; an active semiconductor layer including a channel region, a source doping region and a drain doping region of each transistor in each pixel circuit, the pixel circuit includes a driving transistor, a data writing transistor, a storage capacitor, a threshold compensation transistor, a first reset transistor, a light-emitting device; a first light-blocking pattern arranged on a side of the active semiconductor layer away from the base, an orthographic projection of the first light-blocking pattern on the base covers orthographic projections of channel regions of the first reset transistor and the threshold compensation transistor on the base.

Abstract: The present disclosure provides a display substrate, a manufacturing method and a display device. The display substrate includes a display region, and a non-display region surrounding the display region and including an encapsulation adhesive region surrounding the display region. The display substrate further includes an encapsulation base layer arranged at the encapsulation adhesive region; and a fanout layer arranged at the non-display region and including a first reuse portion. An orthogonal projection of the first reuse portion onto a base substrate of the display substrate at least partially overlaps an orthogonal projection of a first target region of the encapsulation adhesive region onto the base substrate, and the first reuse portion is reused as the encapsulation base layer at the first target region.

Abstract: Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic metal oxide particles, such as ceria-coated silica; and dual chemical additives for providing the tunable oxide film removal rates and tunable SiN film removal rates. Chemical additives comprise at least one nitrogen-containing aromatic heterocyclic compound and at least one non-ionic organic molecule having more than one hydroxyl functional group organic.

Abstract: A display panel has a display area and a peripheral area surrounding the display area, and the peripheral area includes a first sub-peripheral area. A power loop line includes a sub-loop line. Each power connection line is electrically connected to the sub-loop line and a power bus. The at least two power connection lines are divided into two groups that are respectively located on two sides of a division line of the display panel. A plurality of data selectors are divided into two groups that are respectively located on the two sides of the division line. In at least one power connection line in a group and data selectors in a group that are all located on a same side of the division line, the at least one power connection line each passes through a gap between adjacent data selectors to connect the sub-loop line and the power bus.

Abstract: A display substrate and a display device are provided, which includes: a base substrate, a plurality of reset signal lines and a first electrode layer, the first electrode layer includes a plurality of first power supply voltage lines, a plurality of first signal lines, a plurality of first transfer electrodes, a plurality of second transfer electrodes and a plurality of third transfer electrodes, a value of a ratio of an area of an overlapping portion of an orthographic projection of the first body sub-portion and an orthographic projection of the first electrode layer on the board surface of the base substrate, and an area of an overlapping portion of an orthographic projection of the second body sub-portion on the board surface of the base substrate and the orthographic projection of the first electrode layer on the board surface of the base substrate ranges from 0.82 to 1.02.

Abstract: Embodiments of the present disclosure provide a display panel, a display device including the display panel and a method for fabricating the display panel. The display panel comprises a display area and a non-display area surrounding the display area. The display panel includes a pixel array, an edge of which defines a boundary between the display area and the non-display area, wherein the non-display area includes a first area and a second area arranged in sequence in a direction away from the pixel array; a compensation circuit configured to compensate for a parasitic capacitance of pixel in the pixel array, and including a first portion located in the first area and a second portion located in the second area; and a first shift register located in the second area. The second portion of the compensation circuit is aligned with the first shift register circuit in a circumferential direction of the pixel array.

Abstract: High oxide film removal rate Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods, and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic oxide particles, such as ceria-coated silica; and a chemical additive for providing a high oxide film removal rate. The chemical additive is a gelatin molecule possessing negative and positive charges on the same molecule.

Abstract: The present invention provides Chemical Mechanical Planarization Polishing (CMP) compositions for Shallow Trench Isolation (STI) applications. The CMP compositions contain ceria coated inorganic metal oxide particles as abrasives, such as ceria-coated silica particles; chemical additive selected from the first group of non-ionic organic molecules multi hydroxyl functional groups in the same molecule; chemical additives selected from the second group of aromatic organic molecules with sulfonic acid group or sulfonate salt functional groups and combinations thereof; water soluble solvent; and optionally biocide and pH adjuster; wherein the composition has a pH of 2 to 12, preferably 3 to 10, and more preferably 4 to 9.

Abstract: A display substrate and a display device are provided. The display substrate includes a first sub-pixel, a second sub-pixel and a third sub-pixel; each sub-pixel includes a light-emitting region; in at least one of the first sub-pixel, the second sub-pixel and the third sub-pixel, vertex angles of the light-emitting region include a first corner and a second corner opposite to each other; a distance from an intersection of the extension lines or tangents of two sides forming the first corner to a center of the sub-pixel is greater than a distance from an intersection of two sides forming the second corner or the extension lines or tangents thereof to the center; the sub-pixel includes a first-type sub-pixel and a second-type sub-pixel; and in different types of sub-pixels, the direction of the vertex of the first corner pointing to the vertex of the second corner is different.

Abstract: Disclosed is a display substrate, including: a base including a display region and a peripheral region; sub-pixels in the display region; data lines in at least the display region and extending in a first direction and electrically connected to the sub-pixels gate lines in at least the display region and extending in a second direction intersecting with the first direction electrically connected to the sub-pixels pads in the peripheral region; data leads in the peripheral region and electrically connected to the data lines and the pads; a gate driver circuit in the peripheral region and electrically connected to the gate lines; gate drive lines in the peripheral region and electrically connected to the gate driver circuit; gate leads in the peripheral region and extending in the first direction, which are electrically connected to the gate drive lines and the pads and located between the data leads.