Abstract: A display substrate and a display device are provided, which includes: a base substrate, a plurality of reset signal lines and a first electrode layer, the first electrode layer includes a plurality of first power supply voltage lines, a plurality of first signal lines, a plurality of first transfer electrodes, a plurality of second transfer electrodes and a plurality of third transfer electrodes, a value of a ratio of an area of an overlapping portion of an orthographic projection of the first body sub-portion and an orthographic projection of the first electrode layer on the board surface of the base substrate, and an area of an overlapping portion of an orthographic projection of the second body sub-portion on the board surface of the base substrate and the orthographic projection of the first electrode layer on the board surface of the base substrate ranges from 0.82 to 1.02.

Abstract: A method for developing or improving a process for producing a product from a material comprising steps of acquiring the composition for at least two slurries as raw material data (17) for the CMP based manufacturing process and its relevant parameters (2) by using a Data Collecting computer (9); physically performing specific method steps of a CMP process; measuring relevant parameters of the used slurries and the physically performed CMP process to determine the CMP process performance by using the Data Collecting computer (9); analyzing the measured data about the relevant parameters with a specific software performed on an Analyzing computer (11) by creating for the software and applying with it a predictive model using Machine Learning to understand the intercorrelation of the different parameters and using the results to improve the CMP process performance and the resulting product quality of the CMP based manufacturing process.

Abstract: The present disclosure provides a touch circuit, a touch panel and a display device. The touch circuit includes: a plurality of touch signal lines electrically connected with a control circuit, a voltage signal line for providing a preset voltage, and a plurality of switching circuits in one to one correspondence with the touch signal lines, wherein each switching circuit of the plurality of the switching circuits is electrically connected with the corresponding touch signal line and the voltage signal line, the switching circuit is configured to be in an off state under a condition that a voltage value on the corresponding touch signal line is within a preset range, and is also configured to be in an on state under a condition that the voltage value on the corresponding touch signal line is not within the preset range.

Abstract: A method for image display in a display apparatus is provided. The method includes displaying an image in a respective subpixel in an image display phase. In a sensing phase subsequent to the image display phase, the method further includes providing an initial voltage signal to an anode of a respective light emitting element in the respective subpixel for a first period of time; allowing the anode of a respective light emitting element to discharge for a second period of time, upon discontinuation of the initial voltage signal; obtaining a residual voltage signal at the anode of the respective light emitting element at an end of the second period of time by a sensing sub-circuit of a respective pixel driving circuit; and transmitting the residual voltage signal to an integrated circuit.

Abstract: Polishing compositions comprising ceria coated silica particles and organic acids having one selected from the group consisting of sulfonic acid group, phosphonic acid group, pyridine compound, and combinations thereof, with pH between 5 and 10 and electrical conductivity between 0.2 and 10 millisiemens per centimeter provide very high silicon oxide removal rates for advanced semiconductor device manufacturing.

Abstract: Provided are a display substrate and a display apparatus. The display substrate includes a display region and a non-display region surrounding the display region. The display region includes at least an arc-shaped display boundary; the display region includes multiple sub-pixels, multiple data lines extending along a first direction and multiple gate lines extending along a second direction; each sub-pixel includes a pixel circuit and a light emitting element connected to the pixel circuit, the pixel circuit in each sub-pixel is electrically connected to a gate line and a data line respectively; at least part of sub-pixels near the arc-shaped display boundary are disposed in a terraced manner. The non-display region includes multiple cascaded drive circuits which provide drive signals to the multiple gate lines, at least part of drive circuits near the arc-shaped display boundary are disposed in a terraced manner, the first direction intersects with the second direction.

Abstract: A display substrate and a manufacturing method therefor, and a display device. The display substrate includes a display region and a non-display region surrounding the display region, the non-display region includes a wire having a corner; and the display substrate further includes at least one electrostatic protection circuit, the electrostatic protection circuit is electrically connected with the wire at the corner, and the electrostatic protection circuit is configured to eliminate static electricity generated at the corner.

Abstract: A display substrate and a display apparatus are disclosed. The display substrate includes a display region and a peripheral region, the peripheral region includes a circuit region, and the display region includes a plurality of sub-pixels, a plurality of data lines extending along a first direction and a plurality of gate lines extending along a second direction crossing the first direction. The circuit region includes a plurality of driving unit groups. The circuit region includes a first sub-region and a second sub-region that are opposite to each other at two sides of the display region along the first direction, the first sub-region includes a plurality of multiplexing unit groups and the second sub-region includes a plurality of test unit groups.

Abstract: Chemical mechanical planarization (CMP) polishing compositions, methods and systems are provided to reduce oxide trench dishing and improve over-polishing window stability. High and tunable silicon oxide removal rates, low silicon nitride removal rates, and tunable SiO2:SiN selectivity are also provided. The compositions use a unique combination of abrasives such as ceria coated silica particles and chemical additives such as maltitol, lactitol, maltotritol or combinations as oxide trench dishing reducing additives.

Abstract: Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic oxide particles, such as ceria-coated silica; and dual chemical additives for providing the tunable oxide film removal rates and tunable SiN film removal rates; low oxide trench dishing, and high oxide: SiN selectivity. Dual chemical additives comprise at least one silicone-containing compound comprising at least one of (1) ethylene oxide and propylene oxide (EO-PO) group, and at least one of substituted ethylene diamine group on the same molecule; and (2) at least one non-ionic organic molecule having at least two, preferably at least four hydroxyl functional groups.

Abstract: Chemical mechanical planarization (CMP) polishing compositions, methods and systems are provided to reduce oxide trench dishing and improve over-polishing window stability. High and tunable silicon oxide removal rates, low silicon nitride removal rates, and tunable SiO2:SiN selectivity are also provided. The compositions use unique chemical additives, such as maltitol, lactitol, maltotritol, ribitol, D-sorbitol, mannitol, dulcitol, iditol, D-(?)-Fructose, sorbitan, sucrose, ribose, Inositol, glucose, D-arabinose, L-arabinose, D-mannose, L-mannose, meso-erythritol, beta-lactose, arabinose, or combinations thereof as oxide trench dishing reducing additives.

Abstract: A display substrate includes: a base substrate having a display region and a peripheral region surrounding the display region; a plurality of sub-pixels in the display region; a plurality of data lines in the display region, electrically coupled to the plurality of sub-pixels respectively, and configured to provide a data signal to the plurality of sub-pixels respectively; a plurality of pads in the peripheral region, wherein at least a portion of the plurality of pads are configured to provide a data signal to the plurality of data lines respectively; at least one test data signal line in the peripheral region; at least one test control signal line in the peripheral region; and a plurality of test units in the peripheral region and on a side of the plurality of pads away from the display region.

Abstract: A display substrate, a method for manufacturing the display substrate and a display device are provided. The display substrate includes an Electric Test (ET) region. At least one testing pad and an insulation structure surrounding the testing pad are arranged in the ET region, and a distance between a surface of the insulation structure distal to a base substrate of the display substrate and the base substrate is not greater than a distance between a surface of the testing pad distal to the base substrate and the base substrate.

Abstract: A display substrate and display apparatus are provided. The display substrate includes: a base substrate, including a display area and a bezel area; a plurality of pixel units located in the display area and arranged in an array along a row direction and a column direction on the base substrate; a plurality of scanning signal lines; a gate driver circuit located in the bezel area; a plurality of load compensation units located in the bezel area, the plurality of load compensation units are located between the gate driver circuit and the plurality of pixel units; and a plurality of scanning signal lead wires located in the bezel area and configured to transmit a scanning signal output by the gate driver circuit to the scanning signal lines, where at least one of the scanning signal lead wires crosses at least one of the load compensation units in the row direction.

Abstract: A display substrate and a display device are provided. The display substrate includes: a base substrate including a display area (AA) and a peripheral area (PA); a plurality of sub-pixels (Pxl); a plurality of pins a plurality of leads located in the peripheral area (PA), wherein the plurality of pins electrically connected to the plurality of sub-pixels (Pxl) through the plurality of leads ; a plurality of extension pads electrically connected to the plurality of pins; and a plurality of spacers configured to electrically insulate the plurality of extension pads from each other , wherein orthographic projections of the plurality of spacers on the base substrate do not overlap orthographic projections of the plurality of extension pads on the base substrate .

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes: a base; multiple pixel units arranged in multiple rows along a first direction and multiple columns along a second direction and arranged on the base, and each pixel unit includes multiple sub-pixels, each sub-pixel includes a pixel circuit; an active semiconductor layer including a channel region, a source doping region and a drain doping region of each transistor in each pixel circuit, the pixel circuit includes a driving transistor, a data writing transistor, a storage capacitor, a threshold compensation transistor, a first reset transistor, a light-emitting device; a first light-blocking pattern arranged on a side of the active semiconductor layer away from the base, an orthographic projection of the first light-blocking pattern on the base covers orthographic projections of channel regions of the first reset transistor and the threshold compensation transistor on the base.

Abstract: The present disclosure provides a display substrate, a manufacturing method and a display device. The display substrate includes a display region, and a non-display region surrounding the display region and including an encapsulation adhesive region surrounding the display region. The display substrate further includes an encapsulation base layer arranged at the encapsulation adhesive region; and a fanout layer arranged at the non-display region and including a first reuse portion. An orthogonal projection of the first reuse portion onto a base substrate of the display substrate at least partially overlaps an orthogonal projection of a first target region of the encapsulation adhesive region onto the base substrate, and the first reuse portion is reused as the encapsulation base layer at the first target region.

Abstract: Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic metal oxide particles, such as ceria-coated silica; and dual chemical additives for providing the tunable oxide film removal rates and tunable SiN film removal rates. Chemical additives comprise at least one nitrogen-containing aromatic heterocyclic compound and at least one non-ionic organic molecule having more than one hydroxyl functional group organic.

Abstract: A display panel has a display area and a peripheral area surrounding the display area, and the peripheral area includes a first sub-peripheral area. A power loop line includes a sub-loop line. Each power connection line is electrically connected to the sub-loop line and a power bus. The at least two power connection lines are divided into two groups that are respectively located on two sides of a division line of the display panel. A plurality of data selectors are divided into two groups that are respectively located on the two sides of the division line. In at least one power connection line in a group and data selectors in a group that are all located on a same side of the division line, the at least one power connection line each passes through a gap between adjacent data selectors to connect the sub-loop line and the power bus.

Abstract: A display substrate and a display device are provided, which includes: a base substrate, a plurality of reset signal lines and a first electrode layer, the first electrode layer includes a plurality of first power supply voltage lines, a plurality of first signal lines, a plurality of first transfer electrodes, a plurality of second transfer electrodes and a plurality of third transfer electrodes, a value of a ratio of an area of an overlapping portion of an orthographic projection of the first body sub-portion and an orthographic projection of the first electrode layer on the board surface of the base substrate, and an area of an overlapping portion of an orthographic projection of the second body sub-portion on the board surface of the base substrate and the orthographic projection of the first electrode layer on the board surface of the base substrate ranges from 0.82 to 1.02.