Patents by Inventor Hongmei Wang

Hongmei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210193314
    Abstract: Systems, apparatuses, and methods related to medical device data analysis are described. In some examples, a medical device is implanted in a user of the medical device and the data generated by the medical device is not easily accessible to the user. In an example, a controller can be configured to receive, by a mobile device coupled to a medical device, data from the medical device, where the data is a part of a baseline dataset related to the medical device. The controller can be configured to receive different data from the medical device, where the different data is received from the medical device as the different data is generated by the medical device, analyze the data from the medical device and the different data generated by the medical device, and perform an action based on the analyzed data and the different data generated by the medical device.
    Type: Application
    Filed: August 10, 2020
    Publication date: June 24, 2021
    Inventors: Gitanjali T. Ghosh, Irene K. Thompson, Jessica M. Maderos, Hongmei Wang, Fatma Arzum Simsek-Ege, Kathryn H. Russo
  • Publication number: 20210183421
    Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.
    Type: Application
    Filed: October 30, 2020
    Publication date: June 17, 2021
    Inventors: Hongmei Wang, Jin Seung Son, Andrea Ghetti
  • Publication number: 20210183440
    Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 17, 2021
    Inventor: Hongmei Wang
  • Publication number: 20210166746
    Abstract: Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Zhongyuan Lu, Christina Papagianni, Hongmei Wang, Robert J. Gleixner
  • Publication number: 20210151103
    Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.
    Type: Application
    Filed: January 26, 2021
    Publication date: May 20, 2021
    Inventors: Mingdong Cui, Hongmei Wang, Michel Ibrahim Ishac
  • Patent number: 10986440
    Abstract: An earbud comprises: a casing in which a sound cavity is provided; a speaker disposed in the sound cavity and dividing the sound cavity into a front sound cavity and a rear sound cavity; and an acoustic structure located in the rear sound cavity. The acoustic structure comprises a first sound guiding wall and a cover plate, the first sound guiding wall is attached to a bottom surface of the rear sound cavity and is configured to, together with at least a part of an inner wall of the casing, constitutes a sound guiding groove, and the cover plate is mounted at an upper opening part of the sound guiding groove, such that the sound guiding groove forms a bass pipe which communicates from the rear sound cavity to at least one aperture of the casing.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: April 20, 2021
    Inventors: Caiyun Hu, Hongmei Wang, Xiaoli Zhao, Kaibo Xing, Huijin Chen
  • Publication number: 20210111226
    Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventors: Fabio Pellizzer, Lorenzo Fratin, Hongmei Wang
  • Patent number: 10930345
    Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mingdong Cui, Hongmei Wang, Michel Ibrahim Ishac
  • Patent number: 10910438
    Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Lorenzo Fratin, Hongmei Wang
  • Patent number: 10884640
    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
  • Publication number: 20200372966
    Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
    Type: Application
    Filed: August 11, 2020
    Publication date: November 26, 2020
    Inventors: Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Hongmei Wang
  • Publication number: 20200350371
    Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 5, 2020
    Inventors: Fabio Pellizzer, Lorenzo Fratin, Hongmei Wang
  • Patent number: 10777291
    Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Hongmei Wang
  • Patent number: 10748615
    Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hongmei Wang, Luca Crespi, Debayan Mahalanabis, Fabio Pellizzer
  • Publication number: 20200216228
    Abstract: Discloses an earphone box and a control method thereof. The earphone box comprises a box body and a box cover, the box body is for containing an earphone and is connected to the box cover through a rotating shaft, and the box cover is rotatable relative to the box body and capable of being stabilized in a state of forming an angle with respect to the box body. The box body is provided therein with an angle detector which is capable of detecting a rotation angle of the rotating shaft and outputting a detected signal. The box body is further provided therein with an earphone box processor. The earphone box processor receives the detected signal, and when determining that a detected angle value indicated by the detected signal matches a preset angle value, outputs an operation instruction corresponding to the matched preset angle value.
    Type: Application
    Filed: May 21, 2019
    Publication date: July 9, 2020
    Applicant: GOERTEK INC.
    Inventors: Jiyuan WANG, Yuge ZHU, Tianrong DAI, Hongmei WANG, Huijin CHEN, Xuemin OU
  • Patent number: 10672500
    Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
  • Patent number: 10650891
    Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
  • Publication number: 20200145749
    Abstract: An earbud comprises: a casing in which a sound cavity is provided; a speaker disposed in the sound cavity and dividing the sound cavity into a front sound cavity and a rear sound cavity; and an acoustic structure located in the rear sound cavity. The acoustic structure comprises a first sound guiding wall and a cover plate, the first sound guiding wall is attached to a bottom surface of the rear sound cavity and is configured to, together with at least a part of an inner wall of the casing, constitutes a sound guiding groove, and the cover plate is mounted at an upper opening part of the sound guiding groove, such that the sound guiding groove forms a bass pipe which communicates from the rear sound cavity to at least one aperture of the casing.
    Type: Application
    Filed: June 25, 2019
    Publication date: May 7, 2020
    Inventors: Caiyun Hu, Hongmei Wang, Xiaoli Zhao, Kaibo Xing, Huijin Chen
  • Publication number: 20200107103
    Abstract: A wireless earphone comprising an in-ear portion which is in contact with a human ear when the wireless earphone is worn. The in-ear portion comprises a wearing surface which couples the human ear canal when the wireless earphone is worn. The in-ear portion is provided with a wearing detection sensor, a sound venting hole and a contact group which are all disposed on the wearing surface. The wearing detection sensor, the sound venting hole and the contact group are all disposed on the wearing surface of the in-ear portion coupling the human ear canal, so that the wearing detection sensor can directly contact the skin of the human body when the earphone is worn, and thus the wearing detection sensor is improved.
    Type: Application
    Filed: May 20, 2019
    Publication date: April 2, 2020
    Inventors: Shuang CHEN, Yuge ZHU, Tianrong DAI, Hongmei WANG, Lin QI
  • Publication number: 20190355418
    Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 21, 2019
    Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug