Patents by Inventor Hongmei Wang
Hongmei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10910438Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.Type: GrantFiled: May 1, 2019Date of Patent: February 2, 2021Assignee: Micron Technology, Inc.Inventors: Fabio Pellizzer, Lorenzo Fratin, Hongmei Wang
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Patent number: 10884640Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.Type: GrantFiled: April 2, 2019Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
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Publication number: 20200372966Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.Type: ApplicationFiled: August 11, 2020Publication date: November 26, 2020Inventors: Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Hongmei Wang
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Publication number: 20200350371Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.Type: ApplicationFiled: May 1, 2019Publication date: November 5, 2020Inventors: Fabio Pellizzer, Lorenzo Fratin, Hongmei Wang
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Patent number: 10777291Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.Type: GrantFiled: February 25, 2019Date of Patent: September 15, 2020Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Hongmei Wang
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Patent number: 10748615Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.Type: GrantFiled: May 22, 2019Date of Patent: August 18, 2020Assignee: Micron Technology, Inc.Inventors: Hongmei Wang, Luca Crespi, Debayan Mahalanabis, Fabio Pellizzer
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Publication number: 20200216228Abstract: Discloses an earphone box and a control method thereof. The earphone box comprises a box body and a box cover, the box body is for containing an earphone and is connected to the box cover through a rotating shaft, and the box cover is rotatable relative to the box body and capable of being stabilized in a state of forming an angle with respect to the box body. The box body is provided therein with an angle detector which is capable of detecting a rotation angle of the rotating shaft and outputting a detected signal. The box body is further provided therein with an earphone box processor. The earphone box processor receives the detected signal, and when determining that a detected angle value indicated by the detected signal matches a preset angle value, outputs an operation instruction corresponding to the matched preset angle value.Type: ApplicationFiled: May 21, 2019Publication date: July 9, 2020Applicant: GOERTEK INC.Inventors: Jiyuan WANG, Yuge ZHU, Tianrong DAI, Hongmei WANG, Huijin CHEN, Xuemin OU
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Patent number: 10672500Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.Type: GrantFiled: May 22, 2019Date of Patent: June 2, 2020Assignee: Micron Technology, Inc.Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Patent number: 10650891Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.Type: GrantFiled: May 22, 2019Date of Patent: May 12, 2020Assignee: Micron Technology, Inc.Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Publication number: 20200145749Abstract: An earbud comprises: a casing in which a sound cavity is provided; a speaker disposed in the sound cavity and dividing the sound cavity into a front sound cavity and a rear sound cavity; and an acoustic structure located in the rear sound cavity. The acoustic structure comprises a first sound guiding wall and a cover plate, the first sound guiding wall is attached to a bottom surface of the rear sound cavity and is configured to, together with at least a part of an inner wall of the casing, constitutes a sound guiding groove, and the cover plate is mounted at an upper opening part of the sound guiding groove, such that the sound guiding groove forms a bass pipe which communicates from the rear sound cavity to at least one aperture of the casing.Type: ApplicationFiled: June 25, 2019Publication date: May 7, 2020Inventors: Caiyun Hu, Hongmei Wang, Xiaoli Zhao, Kaibo Xing, Huijin Chen
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Publication number: 20200107103Abstract: A wireless earphone comprising an in-ear portion which is in contact with a human ear when the wireless earphone is worn. The in-ear portion comprises a wearing surface which couples the human ear canal when the wireless earphone is worn. The in-ear portion is provided with a wearing detection sensor, a sound venting hole and a contact group which are all disposed on the wearing surface. The wearing detection sensor, the sound venting hole and the contact group are all disposed on the wearing surface of the in-ear portion coupling the human ear canal, so that the wearing detection sensor can directly contact the skin of the human body when the earphone is worn, and thus the wearing detection sensor is improved.Type: ApplicationFiled: May 20, 2019Publication date: April 2, 2020Inventors: Shuang CHEN, Yuge ZHU, Tianrong DAI, Hongmei WANG, Lin QI
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Publication number: 20190355418Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.Type: ApplicationFiled: May 22, 2019Publication date: November 21, 2019Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Publication number: 20190341122Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.Type: ApplicationFiled: May 22, 2019Publication date: November 7, 2019Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Publication number: 20190324671Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.Type: ApplicationFiled: April 2, 2019Publication date: October 24, 2019Applicant: Intel CorporationInventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
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Publication number: 20190311768Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.Type: ApplicationFiled: May 22, 2019Publication date: October 10, 2019Inventors: Hongmei Wang, Luca Crespi, Debayan Mahalanabis, Fabio Pellizzer
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Patent number: 10403359Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.Type: GrantFiled: March 12, 2018Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Patent number: 10381101Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.Type: GrantFiled: December 20, 2017Date of Patent: August 13, 2019Assignee: Micron Technology, Inc.Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Patent number: 10354729Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.Type: GrantFiled: December 28, 2017Date of Patent: July 16, 2019Assignee: Micron Technology, Inc.Inventors: Hongmei Wang, Luca Crespi, Debayan Mahalanabis, Fabio Pellizzer
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Publication number: 20190206489Abstract: Methods, systems, and devices for polarity-conditioned memory cell write operations are described. A memory cell may be written with a logic state by performing a write operation that includes applying a first write voltage across the memory cell with a first polarity, and applying a second write voltage across the memory cell after applying the first write voltage of the write operation, the second write voltage of the write operation having a second polarity that is different than the first polarity. In some examples, performing a write operation on a memory cell having different voltage polarities across the memory call may allow such a write operation to be completed in a shorter time than a write operation having a voltage of a single polarity.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Inventors: Hongmei Wang, Luca Crespi, Debayan Mahalanabis, Fabio Pellizzer
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Publication number: 20190206506Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.Type: ApplicationFiled: February 25, 2019Publication date: July 4, 2019Inventors: Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Hongmei Wang