Patents by Inventor Hongmei Wang
Hongmei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220328104Abstract: The present disclosure includes systems, apparatuses, and methods related to generating a random data value. For example, a first read operation may be performed on a memory cell programmed to a first state, wherein the first read operation is performed using a first read voltage that is within a predetermined threshold voltage distribution corresponding to the first state. A programming signal may be applied to the memory cell responsive to the first read operation resulting in a snapback event, wherein the programming signal is configured to place the memory cell in a second state. A second read operation may be performed to determine whether the memory cell is in the first state or the second state using a second read voltage that is between the predetermined threshold voltage distribution corresponding to the first state and a second threshold voltage distribution corresponding to the second state.Type: ApplicationFiled: April 12, 2021Publication date: October 13, 2022Inventors: Zhongyuan Lu, Hongmei Wang, Robert J. Gleixner
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Patent number: 11430518Abstract: A memory device having memory cells, voltage drivers, and a controller configured to determine, based on an attribute of a memory cell, whether to apply a drift cancellation pulse that is in the opposite polarity of a programming pulse configured to place the memory cell in a state to represent a bit of data. If the drift in the state of the memory cell from a previous programming operation to write data into the memory cell is predicted to be insufficient to prevent the selection of the memory cell during the application of the programming pulse, the drift cancellation pulse is skipped. Otherwise, the drift cancellation pulse is applied in the opposite polarity of the programming pulse.Type: GrantFiled: March 30, 2021Date of Patent: August 30, 2022Assignee: Micron Technology, Inc.Inventors: Hongmei Wang, Mingdong Cui, Nevil N. Gajera
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Patent number: 11417375Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.Type: GrantFiled: October 30, 2020Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Hongmei Wang, Jin Seung Son, Andrea Ghetti
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Patent number: 11380394Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.Type: GrantFiled: January 26, 2021Date of Patent: July 5, 2022Assignee: Micron Technology, Inc.Inventors: Mingdong Cui, Hongmei Wang, Michel Ibrahim Ishac
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Publication number: 20220130444Abstract: Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.Type: ApplicationFiled: January 5, 2022Publication date: April 28, 2022Inventors: Zhongyuan Lu, Christina Papagianni, Hongmei Wang, Robert J. Gleixner
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Publication number: 20220093190Abstract: Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.Type: ApplicationFiled: September 28, 2021Publication date: March 24, 2022Inventors: Karthik Sarpatwari, Nevil N. Gajera, Hongmei Wang, Mingdong Cui
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Publication number: 20220076770Abstract: An example apparatus can include a memory array and control circuitry. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The control circuitry can be configured to designate the first portion as active responsive to a determination that the first portion passed a performance test. The control circuitry can be configured to designate the second portion as inactive responsive to a determination that the second portion failed the performance test.Type: ApplicationFiled: September 4, 2020Publication date: March 10, 2022Inventors: Hongmei Wang, Nevil N. Gajera, Mingdong Cui, Fabio Pellizzer
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Patent number: 11244717Abstract: Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.Type: GrantFiled: December 2, 2019Date of Patent: February 8, 2022Assignee: Micron Technology, Inc.Inventors: Zhongyuan Lu, Christina Papagianni, Hongmei Wang, Robert J. Gleixner
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Patent number: 11217322Abstract: Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage—a setback voltage—of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.Type: GrantFiled: August 11, 2020Date of Patent: January 4, 2022Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Hongmei Wang
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Patent number: 11139034Abstract: Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.Type: GrantFiled: July 15, 2020Date of Patent: October 5, 2021Assignee: Micron Technology, Inc.Inventors: Karthik Sarpatwari, Nevil N. Gajera, Hongmei Wang, Mingdong Cui
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Patent number: 11122352Abstract: A wireless earphone comprising an in-ear portion which is in contact with a human ear when the wireless earphone is worn. The in-ear portion comprises a wearing surface which couples the human ear canal when the wireless earphone is worn. The in-ear portion is provided with a wearing detection sensor, a sound venting hole and a contact group which are all disposed on the wearing surface. The wearing detection sensor, the sound venting hole and the contact group are all disposed on the wearing surface of the in-ear portion coupling the human ear canal, so that the wearing detection sensor can directly contact the skin of the human body when the earphone is worn, and thus the wearing detection sensor is improved.Type: GrantFiled: May 20, 2019Date of Patent: September 14, 2021Assignee: GOERTEK INC.Inventors: Shuang Chen, Yuge Zhu, Tianrong Dai, Hongmei Wang, Lin Qi
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Patent number: 11100986Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.Type: GrantFiled: December 17, 2019Date of Patent: August 24, 2021Assignee: Micron Technology, Inc.Inventor: Hongmei Wang
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Publication number: 20210193314Abstract: Systems, apparatuses, and methods related to medical device data analysis are described. In some examples, a medical device is implanted in a user of the medical device and the data generated by the medical device is not easily accessible to the user. In an example, a controller can be configured to receive, by a mobile device coupled to a medical device, data from the medical device, where the data is a part of a baseline dataset related to the medical device. The controller can be configured to receive different data from the medical device, where the different data is received from the medical device as the different data is generated by the medical device, analyze the data from the medical device and the different data generated by the medical device, and perform an action based on the analyzed data and the different data generated by the medical device.Type: ApplicationFiled: August 10, 2020Publication date: June 24, 2021Inventors: Gitanjali T. Ghosh, Irene K. Thompson, Jessica M. Maderos, Hongmei Wang, Fatma Arzum Simsek-Ege, Kathryn H. Russo
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Publication number: 20210183440Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Inventor: Hongmei Wang
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Publication number: 20210183421Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.Type: ApplicationFiled: October 30, 2020Publication date: June 17, 2021Inventors: Hongmei Wang, Jin Seung Son, Andrea Ghetti
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Publication number: 20210166746Abstract: Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.Type: ApplicationFiled: December 2, 2019Publication date: June 3, 2021Inventors: Zhongyuan Lu, Christina Papagianni, Hongmei Wang, Robert J. Gleixner
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Publication number: 20210151103Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.Type: ApplicationFiled: January 26, 2021Publication date: May 20, 2021Inventors: Mingdong Cui, Hongmei Wang, Michel Ibrahim Ishac
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Patent number: 10986440Abstract: An earbud comprises: a casing in which a sound cavity is provided; a speaker disposed in the sound cavity and dividing the sound cavity into a front sound cavity and a rear sound cavity; and an acoustic structure located in the rear sound cavity. The acoustic structure comprises a first sound guiding wall and a cover plate, the first sound guiding wall is attached to a bottom surface of the rear sound cavity and is configured to, together with at least a part of an inner wall of the casing, constitutes a sound guiding groove, and the cover plate is mounted at an upper opening part of the sound guiding groove, such that the sound guiding groove forms a bass pipe which communicates from the rear sound cavity to at least one aperture of the casing.Type: GrantFiled: June 25, 2019Date of Patent: April 20, 2021Inventors: Caiyun Hu, Hongmei Wang, Xiaoli Zhao, Kaibo Xing, Huijin Chen
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Publication number: 20210111226Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.Type: ApplicationFiled: December 22, 2020Publication date: April 15, 2021Inventors: Fabio Pellizzer, Lorenzo Fratin, Hongmei Wang
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Patent number: 10930345Abstract: An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.Type: GrantFiled: October 22, 2019Date of Patent: February 23, 2021Assignee: Micron Technology, Inc.Inventors: Mingdong Cui, Hongmei Wang, Michel Ibrahim Ishac