Abstract: Methods and systems for processing audio signals are disclosed herein. Aspects of the method may comprise controlling gain during multipath, multi-rate audio processing by generating a digital signal that is a product of an input digital signal and a gain coefficient derived from a lookup table, and coarse tuning the gain by bit-shifting the digital signal to generate a digital output signal. The gain may be fine-tuned utilizing a variable step size determined by interpolation. The gain coefficient may be partitioned into gain blocks, which may be twice a corresponding value in preceding gain blocks. The gain blocks may be partitioned into steps that represent particular gain values within a range associated with the gain block. The digital output signal may be ramped utilizing a linear interpolation of the gain coefficients over a number of samples of the input signal, where the number of samples is given as a power of two.

Abstract: Aspects of a method and/or system for processing high quality audio in a hardware audio CODEC for audio transmission are provided. In this regard, an audio signal may be down-sampled via a cascaded plurality of filters and sample rate converters in the hardware audio CODEC. Additionally, a portion of each sample of the audio signal may be selected based on an origin of the audio signal. The selected portion of each sample of the audio signal may comprise 16 or 18 bits. The selected portion may be determined based on a type, a class, a manufacturer identifier, and/or a model identifier of the origin the audio signal. Coefficients of the filters may be configured based on the origin of the audio signal. One or more of the filters may comprise one or more cascaded biquads. The sample rate converters may comprise one or more CIC decimation filters.

Abstract: Disclosed are various embodiments for cancellation of a PSCH signal and/or SSCH signal from an RX input signal. A PSCH sequence and SSCH sequence are extracted a PSCH and SSCH signal. A relative gain associated with the PSCH signal and SSCH signal are determined relative to a CPICH signal. A reconstructed PSCH and SSCH signal are generated and cancelled from the RX input signal.

Abstract: Certain aspects of a method and system for delay matching in a rake receiver are disclosed. Aspects of one method may include compensating for a delay associated with at least one or both of the following in a rake receiver: a control channel and a data channel, prior to individual processing of received data by the data channel and individual processing of received data by the control channel. The data channel or the dedicated physical channel (DPCH) may be delayed with respect to the control channel, which may comprise, for example, the common pilot control channel (CPICH), by a particular time period.

Abstract: Disclosed are various embodiments providing carrier separation to effectuate a dual carrier operation of a wireless communication device. Processing circuitry may acquire a single carrier signal based on a determined time slot boundary, the single carrier signal comprising primary carrier data. The processing circuitry may receive a dual carrier radio frequency signal based on the determined time slot boundary, the dual carrier radio frequency signal comprising the primary carrier data and secondary carrier data. The processing circuitry may then generate a baseband dual carrier signal by demodulating the dual carrier radio frequency signal. The processing circuitry may separate the primary carrier data from the baseband dual carrier signal by filtering the baseband dual carrier signal. The processing circuitry may also separate the secondary carrier data from the baseband dual carrier signal by filtering the baseband dual carrier signal.

Abstract: Disclosed are various embodiments providing carrier separation to effectuate a dual carrier operation of a wireless communication device. Processing circuitry may acquire a single carrier signal based on a determined time slot boundary, the single carrier signal comprising primary carrier data. The processing circuitry may receive a dual carrier radio frequency signal based on the determined time slot boundary, the dual carrier radio frequency signal comprising the primary carrier data and secondary carrier data. The processing circuitry may then generate a baseband dual carrier signal by demodulating the dual carrier radio frequency signal. The processing circuitry may separate the primary carrier data from the baseband dual carrier signal by filtering the baseband dual carrier signal. The processing circuitry may also separate the secondary carrier data from the baseband dual carrier signal by filtering the baseband dual carrier signal.

Abstract: Disclosed are various embodiments providing carrier separation to effectuate a dual carrier operation of a wireless communication device. Processing circuitry may acquire a single carrier signal based on a determined time slot boundary, the single carrier signal comprising primary carrier data. The processing circuitry may receive a dual carrier radio frequency signal based on the determined time slot boundary, the dual carrier radio frequency signal comprising the primary carrier data and secondary carrier data. The processing circuitry may then generate a baseband dual carrier signal by demodulating the dual carrier radio frequency signal. The processing circuitry may separate the primary carrier data from the baseband dual carrier signal by filtering the baseband dual carrier signal. The processing circuitry may also separate the secondary carrier data from the baseband dual carrier signal by filtering the baseband dual carrier signal.

Abstract: A channel receiver operable to implement fractional dedicated physical channel (F-DPCH) for high-speed data packet access is provided. A received RF signal is processed to produce a set of soft symbol outputs. The receiver detects whether transmit power control (TPC) command bits are present in the set of soft symbol outputs. The TPC command bits are conveyed with the RF signal over non-dedicated pilot bits in the processed baseband signal. When TPC command bits are detected, the set of soft symbol outputs are processed to produce estimated TPC command bits. A TPC quality estimate is generated based on the estimated TPC command bits. A signal-to-interference ratio for the WCDMA dedicated physical channel is adjusted based upon a comparison of the TPC quality estimate with a TPC quality target to effect F-DPCH power control.

Abstract: Certain aspects of a method and system for a delay locked loop for a rake receiver are disclosed. Aspects of one method may include normalizing a signal power of a first control channel based on a threshold value. A sampling time associated with at least one or more of the following: the first control channel, a second control channel, an on-time control channel, and a data channel, may be adjusted based on a comparison between the normalized signal power of the first control channel and a signal power of the second control channel. The second control channel may be delayed with respect to the first control channel by a particular time period. The first and second control channels may be common pilot control channels (CPICHs). The combined signal power of the first control channel may be normalized based on said threshold value.

Abstract: Aspects of a method and system for interference suppression in WCDMA systems may include one or more circuits that are operable to receive a plurality of multipath signals via one or more receiving antennas. A plurality of weighting factor values may be computed based on the received multipath signals. Estimated signals may be based on the weighting factor values. Residual signals may be generated based on received signals and the estimated signals. Addback signals may be generated based on the estimated signals and the residual signals. Updated estimated signals may be generated based on the addback signals and the weighting factor values. Incremental signals may be generated based on the updated estimated signals and addback signals. Updated residual signals may be generated based on the incremental signals and previous residual signals. The interference suppressed signals may be generated based on the updated residual signals and updated estimated signals.

Abstract: Aspects of a method and system for detecting interrupts from detachable electronic accessories or peripherals are provided. In this regard, a hardware audio CODEC may be operable to compare a voltage on one or more biased pins of an accessory or peripheral port to one or more reference voltages and filter one or more output signals generated from the comparison. When an accessory or peripheral is coupled to the accessory or peripheral port, interrupts from the accessory or peripheral may be detected based on results of the comparison and/or the filtering. An interrupt may be detected when the voltage on the one or more pins may be below the one or more reference voltages. An interrupt may be detected when the voltage on the one or more pins may be below the one or more reference voltages for a plurality of consecutive clock cycles.

Abstract: Disclosed are various embodiments for cancellation of a PSCH signal and/or SSCH signal from an RX input signal. A PSCH sequence and SSCH sequence are extracted a PSCH and SSCH signal. A relative gain associated with the PSCH signal and SSCH signal are determined relative to a CPICH signal. A reconstructed PSCH and SSCH signal are generated and cancelled from the RX input signal.

Abstract: Aspects of a method and system for detecting and identifying electronic accessories or peripherals utilizing a hardware audio CODEC are provided. In this regard, a hardware audio CODEC may be operable to compare one or more voltages on one or more biased pins of an accessory or peripheral port to one or more reference voltages and generate one or more digital representations of the one or more voltages on the biased one or more pins. An accessory or peripheral attached to the accessory or peripheral port may be identified based on the comparison and/or the generated one or more digital representations. The one or more bias voltages may be controlled based on a result of the comparison and/or the generated digital representations. The one or more bias voltages may be reduced after an attached accessory or peripheral has been identified.

Abstract: A downlink channel receiver operable to implement fractional dedicated physical channel (F-DPCH) processing within a Rake receiver structure is provided. The downlink channel receiver includes a receiver, a baseband processing block, a WCDMA processing block, wherein F-DPCH processing is divided between a plurality of hardware processing blocks and a plurality of firmware (FW) processing blocks. The receiver is operable to convert a radio frequency (RF) signal to a baseband signal. The baseband processing block operable to processes and provides the baseband signal to the WCDMA processing block. F-DPCH processing is divided between the plurality of hardware processing blocks and plurality of firmware (FW) processing blocks.

Abstract: A system and method for determining the performance of a channel emulator includes an input signal, at least one transmitter configured to receive the input signal, the at least one transmitter coupled to at least one receiver through the channel emulator, the at least one transmitter configured to transmit the input signal through the channel emulator, the at least one receiver configured to receive a faded receive signal. The system also comprises a signal processor configured to receive a processor signal and the faded receive signal, the signal processor configured to correlate the processor signal and the faded receive signal to develop a correlated signal that represents a channel impulse of the channel emulator. The channel impulse of the channel emulator is used to extract at least one channel coefficient that reflects the performance of the channel emulator.

Abstract: Methods and systems for dual digital microphone processing in an audio CODEC are disclosed and may include demultiplexing one or more received time-multiplexed digital audio signals from one or more digital microphones, and separately processing each of the demultiplexed digital audio signals. The digital microphones may include microelectromechanical (MEMS) microphones. The demultiplexed digital audio signals may be level-converted, downshifted, and/or filtered. The filtering may include a finite impulse response (FIR) filter. A sampling rate of the one or more demultiplexed digital audio signals may be converted by repeating the demultiplexed digital audio signals. Audio beamforming and/or diversity processing may be performed utilizing the digital microphones.

Abstract: Aspects of a method and system for UMTS HSDPA Shared Control Channel processing may include calculating at a receiver, for each one of a plurality of control channels, a quality metric based at least one Viterbi Decoder state metric. A control channel may be selected on the basis of the quality metrics, where the quality metric is selected that provides maximum confidence. The selected control channel may be chosen if its corresponding 3GPP metric is greater than a specified threshold, where the threshold is a design parameter. A validity of a selected control channel may be determined based on consistency and a CRC, where the CRC may be derived from decoding a sub-frame. The calculating and selecting may be done for a first slot of a sub-frame for High-Speed Shared Control Channels.

Abstract: Certain aspects of a method and system for a delay locked loop for a rake receiver are disclosed. Aspects of one method may include normalizing a signal power of a first control channel based on a threshold value. A sampling time associated with at least one or more of the following: the first control channel, a second control channel, an on-time control channel, and a data channel, may be adjusted based on a comparison between the normalized signal power of the first control channel and a signal power of the second control channel. The second control channel may be delayed with respect to the first control channel by a particular time period. The first and second control channels may be common pilot control channels (CPICHs). The combined signal power of the first control channel may be normalized based on said threshold value.

Abstract: Aspects of a method and system for a delay-locked loop for closely spaced multipath may include determining a difference signal computed from one or more early energies and one or more late energies associated with one or more channel taps selected from a plurality of channel taps. A fat finger timing may be adjusted based on the difference signal, the fat finger comprising the plurality of channel taps that are spaced contiguously at chip period intervals. The one or more early energies and the one or more late energies may be determined based on an offset of Tc/2 or 3Tc/8, where Tc denotes the chip period interval. The offset may be measured from an energy peak associated with a multipath component that may be associated with the fat finger.

Abstract: Aspects of a method and system for interference suppression in WCDMA systems may include one or more circuits that are operable to receive a plurality of multipath signals via one or more receiving antennas. A plurality of weighting factor values may be computed based on the received multipath signals. Estimated signals may be based on the weighting factor values. Residual signals may be generated based on received signals and the estimated signals. Addback signals may be generated based on the estimated signals and the residual signals. Updated estimated signals may be generated based on the addback signals and the weighting factor values. Incremental signals may be generated based on the updated estimated signals and addback signals. Updated residual signals may be generated based on the incremental signals and previous residual signals. The interference suppressed signals may be generated based on the updated residual signals and updated estimated signals.