Abstract: A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage cells in the storage array; multiple column select signal units that are connected to sensitive amplifiers, the sensitive amplifiers and the multiple bit lines are disposed in one-to-one correspondence; local data buses that are divided into local data buses O and local data buses E, adjacent bit lines are electrically connected to a respective local data bus O and a respective local data bus E, respectively, through a respective sensitive amplifier and a respective column select signal unit; and a first error checking and correcting unit and a second error checking and correcting unit that are configured to check and correct errors of data.

Abstract: A memory is provided. The memory includes banks, each bank includes a U half bank and a V half bank; a first error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of the output data of the U half banks and the V half banks.

Abstract: The present disclosure relates to an amplifier circuit, a control method, and a memory, including: a sensing amplification circuit, including a readout node, a complementary readout node, a first node, and a second node; an isolation circuit, coupled to the readout node, the complementary readout node, a bit line, and a complementary bit line, wherein the isolation circuit is configured to couple the readout node to the bit line and the complementary readout node to the complementary bit line at a sensing amplification stage; an offset cancellation circuit, coupled to the bit line, the complementary bit line, the readout node, and the complementary readout node, wherein the offset cancellation circuit is configured to couple the bit line to the complementary readout node and the complementary bit line to the readout node at an offset cancellation stage; and a processing circuit, coupled to the offset cancellation circuit.

Abstract: Embodiments relate to a semiconductor memory and a method for writing data. The semiconductor memory includes: at least one storage array, the storage array including a plurality of data storage units and a plurality of check bit storage units; a check module, configured to receive written data and generate check data according to the written data; and a data transmission module, respectively connected to the check module and the storage array, the data transmission module being configured to transmit the written data to the plurality of data storage units and transmit the check data to the plurality of check bit storage units. A first transmission time duration of the check data is shorter than a second transmission time duration of the written data.

Abstract: A memory bank includes at least one storage module, each storage module including a read-write control circuit, a column decoding circuit and a plurality of storage arrays, the plurality of storage arrays being divided into a first unit and a second unit; a first decoding selective signal line, electrically connected to the column decoding circuit and the storage arrays in the first unit; a second decoding selective signal line, electrically connected to the column decoding circuit and the storage arrays in the second unit; a first data signal line; and a second data signal line.

Abstract: A package structure includes N first pads, N redistribution layers, second pads and third pads. Each first pad is formed by a interconnect layer exposed by one via hole. Each redistribution layer covers the isolation layer and is electrically connected with a corresponding first pad. Some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, and other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure. The exposed parts of each redistribution layer form a second and a third pad. Both an offset direction and an offset distance between a center point of the second pad and that of a corresponding first pad are same. A relative position between the second pad and the third pad for some redistribution layers is different from that for others.

Abstract: A package structure includes an isolation layer with multiple vias, N first pads, N Redistribution Layers (RDLs), and a first insulating layer. Each via exposes a respective part of an interconnection layer arranged on a surface of a semiconductor functional structure. Each first pad is formed by a respective part of the interconnection layer exposed by the corresponding via, N is a positive integer greater than 1. Each RDL covers the isolation layer and is electrically connected to a corresponding one of the N first pads. The first insulating layer is formed on the RDLs and exposes a part area of each RDL. The exposed part areas of at least some of the RDLs includes second pads and third pads. The center point of each second pad has the same offset direction and the same offset distance with respect to the center point of the corresponding first pad.

Abstract: The present disclosure relates to a memory circuit, a data transmission circuit, and a memory. The memory circuit includes: at least one memory structure arranged parallel to a data transmission region, wherein the memory structure includes a first memory array and a second memory array arranged adjacent to each other in a first direction, a distance between the first memory array and the data transmission region is less than a distance between the second memory array and the data transmission region, and the first direction is a direction of approaching the data transmission region; the first memory array includes a read/write module and a forwarding module; the second memory array includes a read/write module; the first memory array performs a data interaction with the data transmission region based on the read/write module in the first memory array.

Abstract: An amplification circuit includes a sense amplification circuit, including a read node SABL, a complementary read node SABLB, a first node PCS, and a second node NCS; an isolation circuit, coupled to the SABL, the SABLB, a hit line BL, and a complementary hit line BLB, configured to: in a sense amplification stage, couple the SABL to the BL and couple the BLB to the SABLB; an offset cancellation circuit, coupled to the BL, the BLB, the SABL, and the SABLB, configured to: in an offset cancellation stage, couple the BL to the SABLB and couple the BLB to the SABL; and a first power supply circuit, coupled to the PCS, and configured to: acquire memory temperature information, and in the offset cancellation stage, adjust, according to the memory temperature information, a magnitude of a power supply voltage provided to the PCS.

Abstract: An amplification circuit includes: a sense amplification circuit including a read node, a complementary read node, a first node and a second node; an isolation circuit, which couples the read node to a bit line and couples the complementary read node to a complementary bit line in a sense amplification stage; an offset cancellation circuit, which couples the bit line to the complementary read node and couple the complementary bit line to read node in an offset cancellation stage; and a first power supply circuit, coupled to the first node, including a first power supply and a second power supply, a power supply voltage of the first power supply being higher than that of the second power supply, the first power supply circuit couples the first power supply to the first node in offset cancellation stage, and couples the second power supply to the first node in sense amplification stage.

Abstract: The present disclosure relates to an amplifier circuit, a control method, and a memory, including: a sensing amplification circuit, including a readout node, a complementary readout node, a first node, and a second node; an isolation circuit, coupled to the readout node, the complementary readout node, a bit line, and a complementary bit line, wherein the isolation circuit is configured to couple the readout node to the bit line and the complementary readout node to the complementary bit line at a sensing amplification stage; an offset cancellation circuit, coupled to the bit line, the complementary bit line, the readout node, and the complementary readout node, wherein the offset cancellation circuit is configured to couple the bit line to the complementary readout node and the complementary bit line to the readout node at an offset cancellation stage; and a processing circuit, coupled to the offset cancellation circuit.

Abstract: A semiconductor memory includes storage arrays, at least one verification module and gating circuits. Each verification module corresponds to multiple storage arrays. The verification module is configured to verify whether an error occurs in data information of the corresponding storage arrays. Each verification module is connected to a group of global data buses. The gating circuits are respectively connected to the storage arrays and the global data buses, and the gating circuits are configured to control on and off of a data transmission path connecting the global data buses to the storage arrays.

Abstract: The present disclosure provides a memory bank and a memory. The memory bank includes: multiple memory arrays arranged along a first direction, each of the memory arrays being divided into at least two array units along a second direction, and the first direction and the second direction being perpendicular to each other; multiple read-write control circuits, the read-write control circuits being provided between adjacent two of the memory arrays; and multiple data signal lines configured to electrically connect the read-write control circuits and the array units; wherein, different array units of each of the memory arrays are electrically connected to different read-write control circuits through different data signal lines.

Abstract: The present disclosure provides a memory bank and a memory, relating to the technical field of semiconductors. The memory bank includes: multiple memory arrays arranged along a first direction, configured to store data and check codes, and each of the memory arrays being divided into at least two array units; multiple read-write control circuits, in one-to-one correspondence to the memory arrays, and the read-write control circuit being configured to write the data and the check codes to a corresponding memory array or read the data and the check codes from the corresponding memory array; the read-write control circuit being electrically connected to the array units through different data signal lines, and the read-write control circuit being configured to access only one of the array units in the corresponding memory array at a time; and multiple error checking and correcting units, electrically connected to the multiple read-write control circuits.

Abstract: Provided are a data transmission circuit and a memory. The data transmission circuit includes: a normal reading module, which is connected to a normal storage array and configured to read and output data from the normal storage array; a redundant reading module, which is connected to a redundant storage array, and configured to read and output data from the redundant storage array; and an error detection operation module, which is connected to the normal reading module and the redundant reading module respectively, and configured to synchronously receive the read data output from the normal reading module and the redundant reading module, and perform error detection operation on the read data.

Abstract: A memory includes: bit lines extending along a first direction and word lines extending along a second direction; a plurality of memory modules arranged along the first direction; a column selection circuit and a read-write control driver circuit, wherein the column selection circuit and the read-write control driver circuit are located on a same side of the plurality of memory modules perpendicular to the first direction; column-select lines extending along the first direction and column connection lines extending along a third direction, wherein each of the column-select lines is electrically connected to an amplification unit arranged along the first direction and is electrically connected to the column selection circuit through the column connection line, and the column selection circuit is configured to drive the amplification unit electrically connected to the column-select line.

Abstract: A memory includes: bit lines (BLs) extending along a first direction and word lines (WLs) extending along a second direction; a read-write control circuit and a plurality of memory modules that are arranged along the first direction, wherein each of the plurality of memory modules includes a memory array and an amplifier array that are arranged along the first direction, the memory array includes at least one memory cell, the amplifier array includes at least one amplification unit, each of the BLs is electrically connected to a first terminal of a corresponding amplification unit, and each of the WLs is electrically connected to a corresponding memory cell; a column selection circuit, wherein the column selection circuit and the read-write control circuit are located on two adjacent sides of the plurality of memory modules as a whole, respectively; m column-select lines (CSLs) extending along the first direction.

Abstract: Disclosed are a gradient resin, a preparation method therefor and the use thereof. The gradient resin of the present application is formed by fusing different layers with color transition changes, wherein the color transition change between the two adjacent layers is in the range of 0.1% to 5 20%. The gradient resin is composed of, by mass percentage, 98%-99.99% of a resin powder and 0.01%-2% of a pigment.

Abstract: A memory includes: bit lines extending along a first direction and word lines extending along a second direction; a column selection circuit and a plurality of memory modules that are arranged along the first direction; column-select lines extending along the first direction, wherein the column-select lines each are electrically connected to the column selection circuit, and the column selection circuit drives a corresponding amplification unit through one of the column-select lines; a read-write control driver circuit, wherein the read-write control driver circuit and the column selection circuit are located, respectively, on two adjacent sides of the plurality of memory modules as a whole; and a global data line extending along the second direction and an electrical connection line extending along a third direction, wherein the global data line is electrically connected to the read-write control driver circuit through the electrical connection line.

Abstract: Embodiments relate to a data storage circuit and a control method thereof, and a storage apparatus. The data storage circuit includes a first storage array and a sense amplifier array, the first storage array is positioned on a side of the sense amplifier array, and the sense amplifier array is electrically connected to a main bit line. The first storage array includes a plurality of first sub storage arrays, each of the plurality of first sub storage arrays includes a plurality of first sub bit lines and a plurality of first selector switches, each of the plurality of first sub bit lines is electrically connected to the main bit line via one of the plurality of first selector switches, and the sense amplifier array is configured to amplify a signal of the main bit line.