Patents by Inventor Hongwen Li

Hongwen Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220231206
    Abstract: The disclosure provides a light-emitting device and a displayer. Herein, the light-emitting device includes a substrate, a light-emitting chip, a first light-transmitting layer, a second light-transmitting layer and a nano coating. The light transmittance of the second light-transmitting layer is greater than the light transmittance of the first light-transmitting layer. A reference surface corresponding to the light-emitting chip is arranged above the substrate, and the reference surface is higher than the bottom surface of the light-emitting chip and not higher than the top surface of the light-emitting chip. The first light-transmitting layer covers the surface of the light-emitting chip below the reference surface, and the second light-transmitting layer covers the surface of the light-emitting chip above the reference surface. The nano coating covers the outer surface of the first light-transmitting layer, the outer surface of the second light-transmitting layer and the side surface of the substrate.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 21, 2022
    Inventors: Kuai QIN, Heng GUO, Xiaobo OUYANG, Hongwen CHEN, Qiang ZHAO, Bin CAI, Nianpu LI, Junyong WANG
  • Patent number: 11380368
    Abstract: The disclosed chip includes a storage module, pins, a control module, a first connection and a second connection. The storage module includes a first and a second storage array groups, which respectively include a plurality of first storage arrays and a plurality of second storage arrays. The pins are located on the side of the first storage array group away from the second storage array group. The control module is located between the first storage array group and the second storage array group. The first connection pin connects to the control module; and the second connection connects the control module to the first and the second storage array groups. The first connection line has a length less than the distance from the control module to the second storage array group at far side of the control module. The chip reduces the parasitic capacitance introduced by the first connection.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: July 5, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: KangLing Ji, Hongwen Li, Kai Tian
  • Publication number: 20220093159
    Abstract: A DRAM memory includes: a substrate; a plurality of memory banks arranged in rows and columns on the substrate, each memory bank is divided into three memory blocks in the column direction. Each memory block has a number of memory cells arranged in rows and columns. Dividing each memory bank into three memory blocks in the column direction shortens the length of the memory bank in the row direction, as each memory bank has a certain capacity, so a large drive is no longer required. In addition, the distance from the control circuit and the data transmission circuit to the corresponding memory cell in the memory array in each memory bank will be shorter too, reducing parasitic resistance and parasitic capacitance generated from the data transmission circuit. As a result, the data transmission rate and data transmission accuracy are improved. The overall power consumption is reduced.
    Type: Application
    Filed: December 24, 2019
    Publication date: March 24, 2022
    Inventors: Kangling JI, Weibing Shang, Hongwen Li
  • Publication number: 20220093201
    Abstract: A memory is provided. The memory includes banks, each bank includes a U half bank and a V half bank; a first error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of the output data of the U half banks and the V half banks.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 24, 2022
    Inventors: Weibing SHANG, Hongwen LI, Liang ZHANG, Kangling JI, SUNGSOO CHI, Daoxun WU, Ying WANG
  • Publication number: 20220083418
    Abstract: A semiconductor memory includes storage arrays, at least one verification module and gating circuits. Each verification module corresponds to multiple storage arrays. The verification module is configured to verify whether an error occurs in data information of the corresponding storage arrays. Each verification module is connected to a group of global data buses. The gating circuits are respectively connected to the storage arrays and the global data buses, and the gating circuits are configured to control on and off of a data transmission path connecting the global data buses to the storage arrays.
    Type: Application
    Filed: August 26, 2021
    Publication date: March 17, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: KangLing JI, Hongwen LI
  • Publication number: 20220066865
    Abstract: Provided are a data transmission circuit and a memory. The data transmission circuit includes: a normal reading module, which is connected to a normal storage array and configured to read and output data from the normal storage array; a redundant reading module, which is connected to a redundant storage array, and configured to read and output data from the redundant storage array; and an error detection operation module, which is connected to the normal reading module and the redundant reading module respectively, and configured to synchronously receive the read data output from the normal reading module and the redundant reading module, and perform error detection operation on the read data.
    Type: Application
    Filed: September 7, 2021
    Publication date: March 3, 2022
    Inventors: Kangling JI, Hongwen LI
  • Patent number: 11243111
    Abstract: Disclosed is an integrated physiological signal detection sensor, comprising a movable housing member, a fixed housing member, and a sensing unit circuit board. The movable housing member and the fixed housing member are connected to form an internal space therebetween. The sensing unit circuit board is fixedly installed on the fixed housing member within the space. A piezoelectric film is attached to the sensing unit circuit board. A hollowed-out region surrounds the periphery of the piezoelectric film. A protrusion is provided on the movable housing member at a position corresponding to the piezoelectric film. The sensor of the present invention has advantages of simplified sensor installation, improved signal integrity, and simplified wire routing of an electromagnetic shield layer, thereby eliminating errors caused by sensor installation and improving the accuracy of data detection.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: February 8, 2022
    Assignees: Keeson Technology Corporation Limited, ZHEJIANG YANGTZE DELTA REGION INSTITUTE OF TSINGHUA UNIVERSITY
    Inventors: Huafeng Shan, Jiadong Wang, Kaimin Cao, Hongwen Li, Yuan Yu
  • Publication number: 20210407576
    Abstract: A memory bank includes at least one storage module, each storage module including a read-write control circuit, a column decoding circuit and a plurality of storage arrays, the plurality of storage arrays being divided into a first unit and a second unit; a first decoding selective signal line, electrically connected to the column decoding circuit and the storage arrays in the first unit; a second decoding selective signal line, electrically connected to the column decoding circuit and the storage arrays in the second unit; a first data signal line; and a second data signal line.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 30, 2021
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Weibing SHANG, Hongwen LI
  • Publication number: 20210375328
    Abstract: The disclosed chip includes a storage module, pins, a control module, a first connection and a second connection. The storage module includes a first and a second storage array groups, which respectively include a plurality of first storage arrays and a plurality of second storage arrays. The pins are located on the side of the first storage array group away from the second storage array group. The control module is located between the first storage array group and the second storage array group. The first connection pin connects to the control module; and the second connection connects the control module to the first and the second storage array groups. The first connection line has a length less than the distance from the control module to the second storage array group at far side of the control module. The chip reduces the parasitic capacitance introduced by the first connection.
    Type: Application
    Filed: December 11, 2019
    Publication date: December 2, 2021
    Inventors: KangLing JI, Hongwen LI, Kai TIAN
  • Patent number: 11164849
    Abstract: Embodiments provide a chip assembly and a chip. The chip assembly includes a substrate, a first chip and a second chip stacked on an upper surface of the substrate, and the first chip is arranged above the second chip. At edges of first sides of the first chip and the second chip there is provided with a first pad pair, and at edges of second sides of the first chip and the second chip there is provided with a second pad pair. The second pad pair is arranged between two adjacent functional units at an outermost side of the edge of the second side of the first chip or the second chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent functional units.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: November 2, 2021
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kai Tian, Hongwen Li
  • Publication number: 20210265316
    Abstract: Embodiments provide a chip assembly and a chip. The chip assembly includes a substrate, a first chip and a second chip stacked on an upper surface of the substrate, and the first chip is arranged above the second chip. At edges of first sides of the first chip and the second chip there is provided with a first pad pair, and at edges of second sides of the first chip and the second chip there is provided with a second pad pair. The second pad pair is arranged between two adjacent functional units at an outermost side of the edge of the second side of the first chip or the second chip, and a lower edge of the second pad pair is not lower than lower edges of the two adjacent functional units.
    Type: Application
    Filed: March 9, 2021
    Publication date: August 26, 2021
    Inventors: Kai TIAN, Hongwen LI
  • Publication number: 20210225510
    Abstract: Disclosed is a human body health assessment method and assessment system based on sleep big data. The method and the system acquire biometric data of a human body in a long-term, stable, and ever-increasing manner, and clearly and definitely describe the physical conditions of a human being and predict future health thereof using advanced data mining technology. The method comprises: acquiring, by a sensor mounted on a bed, various physiological data of a human body during sleep and storing the same to a cloud server; and obtaining a physiological evaluation index using an artificial intelligence learning model and generating a health status analysis report of the human body. By acquiring the data of the sensor mounted on the bed, data training of the artificial intelligence learning model is performed, to allow the model to automatically learn features related to the health of the human body.
    Type: Application
    Filed: August 17, 2018
    Publication date: July 22, 2021
    Inventors: Xiangdong Yang, Huafeng Shan, Hui Cao, Qilong Song, Hongwen Li, Zhenyu Zhu, Xiuping Han
  • Publication number: 20210215533
    Abstract: Disclosed is an integrated physiological signal detection sensor, comprising a movable housing member, a fixed housing member, and a sensing unit circuit board. The movable housing member and the fixed housing member are connected to form an internal space therebetween. The sensing unit circuit board is fixedly installed on the fixed housing member within the space. A piezoelectric film is attached to the sensing unit circuit board. A hollowed-out region surrounds the periphery of the piezoelectric film. A protrusion is provided on the movable housing member at a position corresponding to the piezoelectric film. The sensor of the present invention has advantages of simplified sensor installation, improved signal integrity, and simplified wire routing of an electromagnetic shield layer, thereby eliminating errors caused by sensor installation and improving the accuracy of data detection.
    Type: Application
    Filed: August 1, 2018
    Publication date: July 15, 2021
    Applicants: Keeson Technology Corporation Limited, ZHEJIANG YANGTZE DELTA REGION INSTITUTE OF TSINGHUA UNIVERSITY
    Inventors: Huafeng Shan, Jiadong Wang, Kaimin Cao, Hongwen Li, Yuan Yu
  • Publication number: 20210174890
    Abstract: Embodiments provide a test circuit and a memory chip. The test circuit is configured to read compressed data of a memory. The test circuit includes M storage blocks, wherein the M is an even number greater than or equal to 2. N storage blocks constitute one storage group, wherein the N is an even number greater than or equal to 2 and less than or equal to the M, and the M is an integral multiple of the N. The test circuit further includes a compressed data reading unit. One compressed data reading unit corresponds to one storage group. The compressed data reading unit is connected to the N storage blocks in the corresponding storage group. The compressed data reading unit receives a compressed data reading command and address information, and reads data in the N storage blocks according to the compressed data reading command and the address information.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 10, 2021
    Inventors: Jia WANG, Liang ZHANG, Hongwen LI
  • Publication number: 20180327319
    Abstract: The application discloses a dental zirconia restoration material with uniform transition of strength and color, and a preparation method thereof. The preparation method includes the following steps: (1) pouring colored zirconia powder into a dry pressing mould in accordance with a sequence of the strength from high to low and the color from dark to light for each layer, and performing dry pressing; (2) performing isostatic cool pressing after the dry pressing; (3) performing pre-sintering after the isostatic cool pressing to obtain a greenware; and (4) performing CAD/CAM cutting on the greenware, and finally performing final sintering to obtain the dental zirconia restoration material. In the present application, the strength of a restoration can gradually increase from a cut end to the neck, the wear to adjacent teeth and jaw teeth is reduced, and long-bridge restoration can be realized due to the high strength of the neck.
    Type: Application
    Filed: August 30, 2017
    Publication date: November 15, 2018
    Applicant: Aidite (Qinhuangdao) Technology Co.Ltd.
    Inventors: Hongwen LI, Haiyan WU, Yingying Chen
  • Patent number: 10087260
    Abstract: Disclosed are an anti-HER2 antibody and conjugate of the anti-HER2 antibody and small molecule medicine. Also disclosed are uses of the antibody and conjugate thereof in preparing medicine for treating tumor.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: October 2, 2018
    Assignee: REMEGEN, LTD.
    Inventors: Jianmin Fang, Changjiang Huang, Jing Jiang, Xuejing Yao, Hongwen Li, Qiaoyu Xu, Zhuanglin Li
  • Publication number: 20160304621
    Abstract: Disclosed are an anti-HER2 antibody and conjugate of the anti-HER2 antibody and small molecule medicine. Also disclosed are uses of the antibody and conjugate thereof in preparing medicine for treating tumor.
    Type: Application
    Filed: November 18, 2014
    Publication date: October 20, 2016
    Applicant: REMEGEN, LTD.
    Inventors: Jianmin FANG, Changjiang HUANG, Jing JIANG, Xuejing YAO, Hongwen LI, Qiaoyu XU
  • Publication number: 20090071758
    Abstract: Provided is an elevator car frame, comprising: an elevator cage, a main elevator car frame comprising a pair of main columns, an upper main beam and a lower main beam, and a pair of diversion sheaves; wherein the main columns are disposed on both sides of the elevator cage; the upper main beam is disposed above the elevator cage; the lower main beam is disposed below the elevator cage; the diversion sheaves are disposed on one side of the upper main beam; and a line connecting centers of the diversion sheaves is parallel to the upper main beam. The invention features increased working space, reduced height of the elevator car roof, and lower cost.
    Type: Application
    Filed: November 18, 2008
    Publication date: March 19, 2009
    Applicant: SHENYANG BRILLIANT ELEVATOR CO., LTD.
    Inventors: Zhigang YU, Yunsong GU, Hetong MAO, Hongwen LI, Junbin LI
  • Publication number: 20090071759
    Abstract: A traction drive elevator, comprising: an elevator car, a pair of guide rails, a counterweight, a traction drive motor comprising a housing, a stator, a rotor and a traction sheave; wherein the guide rails are disposed in a hoistway; both ends of the housing are symmetrically fixed to a side wall of the hoistway; the housing operates as a bearing beam; and the elevator car and the counterweight are suspended on the traction sheave of the traction drive motor via a plurality of wire ropes. Since the traction drive motor occupies no additional vertical space in the hoistway, space utilization ratio of the vertical space in the hoistway is increased, the height of the top floor is decreased, and building materials are saved.
    Type: Application
    Filed: November 18, 2008
    Publication date: March 19, 2009
    Applicant: SHENYANG BRILLIANT ELEVATOR CO., LTD.
    Inventors: Zhigang YU, Yunsong GU, Hetong MAO, Hongwen LI, Junbin LI
  • Publication number: 20060246683
    Abstract: A method is provided that includes (1) receiving information about a substrate processed within a low K dielectric deposition subsystem from an integrated inspection system of the low K dielectric deposition subsystem; (2) determining an etch process to perform within an etch subsystem based at least in part on the information received from the inspection system of the low K dielectric deposition subsystem; and (3) directing the etch subsystem to etch at least one low K dielectric layer on the substrate based on the etch process. Other methods, systems, apparatus, data structures and computer program products are provided.
    Type: Application
    Filed: June 21, 2006
    Publication date: November 2, 2006
    Inventors: Judon Pan, Michael Armacost, Hoiman Hung, Hongwen Li, Arulkumar Shanmugasundram, Moshe Sarfaty, Dimitris Lymberopoulos, Mehul Naik