Patents by Inventor Hongyu Liu

Hongyu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hierarchical cross-point array of non-volatile memory
    Patent number: 8098507
    Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: January 17, 2012
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Insik Jin, YoungPil Kim, Harry Hongyue Liu
  • Computer memory device with status register
    Patent number: 8081504
    Abstract: Method and apparatus for operating a memory device with a status register. In some embodiments, the memory device has a plurality of individually programmable non-volatile memory cells comprised of at least a resistive sense memory. The memory device engages an interface and maintains a status register in some embodiments by logging at least an error or busy signal during data transfer operations.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: December 20, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Hongyue Liu, Hai Li
  • Floating Source Line Architecture for Non-Volatile Memory
    Publication number: 20110299323
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 8, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
  • WRITE CURRENT COMPENSATION USING WORD LINE BOOSTING CIRCUITRY
    Publication number: 20110299324
    Abstract: Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.
    Type: Application
    Filed: August 16, 2011
    Publication date: December 8, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hai Li, Yiran Chen, Harry Hongyue Liu, Henry Huang, Ran Wang
  • Asymmetric Write Current Compensation Using Gate Overdrive for Resistive Sense Memory Cells
    Publication number: 20110292716
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 1, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • Static source plane in stram
    Patent number: 8068359
    Abstract: A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: November 29, 2011
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Hongyue Liu, Xuguang Wang
  • Magnetic tunnel junction and memristor apparatus
    Patent number: 8059453
    Abstract: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: November 15, 2011
    Assignee: Seagate Technology LLC
    Inventors: Xiaobin Wang, Yiran Chen, Alan Wang, Haiwen Xi, Wenzhong Zhu, Hai Li, Hongyue Liu
  • Three dimensionally stacked non volatile memory units
    Patent number: 8054673
    Abstract: A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: November 8, 2011
    Assignee: Seagate Technology LLC
    Inventors: Xuguang Wang, Yong Lu, Hai Li, Hongyue Liu
  • Stuck-at defect condition repair for a non-volatile memory cell
    Patent number: 8054678
    Abstract: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: November 8, 2011
    Assignee: Seagate Technology LLC
    Inventors: Alan Xuguang Wang, Xiaobin Wang, Dimitar V. Dimitrov, Hai Li, Haiwen Xi, Harry Hongyue Liu
  • Variable write and read methods for resistive random access memory
    Patent number: 8054675
    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: November 8, 2011
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li
  • NAND flash memory with integrated bit line capacitance
    Patent number: 8050092
    Abstract: Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of the cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: November 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Harry Hongyue Liu, Brian Lee, Yong Lu, Dadi Setiadi
  • Multi-stage parallel data transfer
    Patent number: 8045412
    Abstract: Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 25, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu, Hai Li, Andrew John Carter, Daniel Reed
  • Bit set modes for a resistive sense memory cell array
    Patent number: 8040713
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: October 18, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman
  • TRANSMISSION GATE-BASED SPIN-TRANSFER TORQUE MEMORY UNIT
    Publication number: 20110228598
    Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
    Type: Application
    Filed: May 31, 2011
    Publication date: September 22, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Yang Li
  • Write current compensation using word line boosting circuitry
    Patent number: 8009457
    Abstract: Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: August 30, 2011
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Harry Hongyue Liu, Henry Huang, Ran Wang
  • Asymmetric write current compensation using gate overdrive for resistive sense memory cells
    Patent number: 8009458
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: August 30, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • Semiconductor Control Line Address Decoding Circuit
    Publication number: 20110205830
    Abstract: Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N?1 output lines.
    Type: Application
    Filed: May 4, 2011
    Publication date: August 25, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Dadi Setiadi, YoungPil Kim, Harry Hongyue Liu, Hyung-Kyu Lee
  • Floating source line architecture for non-volatile memory
    Patent number: 8004872
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: August 23, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
  • MAGNETIC FLOATING GATE MEMORY
    Publication number: 20110199832
    Abstract: An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element.
    Type: Application
    Filed: April 28, 2011
    Publication date: August 18, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Insik Jin, Yang Li, Hongyue Liu, Song S. Xue
  • Non-Volatile Memory Cell With Precessional Switching
    Publication number: 20110194337
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.
    Type: Application
    Filed: April 21, 2011
    Publication date: August 11, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xiaobin Wang, Yong Lu, Haiwen Xi, Yuankai Zheng, Yiran Chen, Harry Hongyue Liu, Dimitar Dimitrov, Wei Tian, Brian Seungwhan Lee