Patents by Inventor Hongyu Liu

Hongyu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100315865
    Abstract: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.
    Type: Application
    Filed: August 24, 2010
    Publication date: December 16, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xuguang Wang, Yiran Chen, Dimitar V. Dimitrov, Hongyue Liu, Xiaobin Wang
  • Patent number: 7852665
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: December 14, 2010
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Ran Wang, Harry Hongyue Liu
  • Publication number: 20100302849
    Abstract: Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 2, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Harry Hongyue Liu, Brian Lee, Yong Lu, Dadi Setiadi
  • Publication number: 20100302839
    Abstract: A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.
    Type: Application
    Filed: August 13, 2010
    Publication date: December 2, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hai Li, Yiran Chen, Hongyue Liu, Xuguang Wang
  • Patent number: 7830708
    Abstract: Method and apparatus for compensating for variations in memory cell programmed state distributions, such as but not limited to a non-volatile memory formed of NAND configured Flash memory cells. In accordance with various embodiments, a memory block is formed from a plurality of memory cells that are arranged into rows and columns within the memory block, each memory cell configured to have a programmed state. A selected row of the memory block is read by concurrently applying a stepped sequence of threshold voltages to each memory cell along the selected row while sequentially decoupling read current from groups of memory cells along the selected row as the programmed states of said groups of cells are successively determined.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: November 9, 2010
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
  • Patent number: 7830700
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: November 9, 2010
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li
  • Patent number: 7830693
    Abstract: Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: November 9, 2010
    Assignee: Seagate Technology LLC
    Inventors: Harry Hongyue Liu, Haiwen Xi, Antoine Khoueir, Song Xue
  • Patent number: 7826255
    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: November 2, 2010
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li
  • Publication number: 20100271875
    Abstract: Method and apparatus for compensating for variations in memory cell programmed state distributions, such as but not limited to a non-volatile memory formed of NAND configured Flash memory cells. In accordance with various embodiments, a memory block is formed from a plurality of memory cells that are arranged into rows and columns within the memory block, each memory cell configured to have a programmed state. A selected row of the memory block is read by concurrently applying a stepped sequence of threshold voltages to each memory cell along the selected row while sequentially decoupling read current from groups of memory cells along the selected row as the programmed states of said groups of cells are successively determined.
    Type: Application
    Filed: April 22, 2009
    Publication date: October 28, 2010
    Applicant: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
  • Publication number: 20100265749
    Abstract: A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
    Type: Application
    Filed: April 16, 2009
    Publication date: October 21, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xuguang Wang, Yong Lu, Hai Li, Hongyue Liu
  • Publication number: 20100246251
    Abstract: A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.
    Type: Application
    Filed: March 30, 2009
    Publication date: September 30, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Harry Hongyue Liu, Dimitar V. Dimitrov, Alan Xuguang Wang, Xiaobin Wang
  • Publication number: 20100246250
    Abstract: Various embodiments are generally directed to a method and apparatus for carrying out a pipeline sensing operation. In some embodiments, a read voltage from a first memory cell is stored in a voltage storage element (VSE) and compared to a reference voltage to identify a corresponding memory state of the first memory cell while a second read voltage from a second memory cell is stored in a second VSE. In other embodiments, bias currents are simultaneously applied to a first set of memory cells from the array while read voltages generated thereby are stored in a corresponding first set of VSEs. The read voltages are sequentially compared with at least one reference value to serially output a logical sequence corresponding to the memory states of the first set of memory cells while read voltages are stored for a second set of memory cells in a second set of VSEs.
    Type: Application
    Filed: March 24, 2009
    Publication date: September 30, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Harry Hongyue Liu, KangYong Kim, Henry F. Huang
  • Patent number: 7804709
    Abstract: A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: September 28, 2010
    Assignee: Seagate Technology LLC
    Inventors: Xuguang Wang, Yiran Chen, Dimitar V. Dimitrov, Hongyue Liu, Xiaobin Wang
  • Publication number: 20100238721
    Abstract: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.
    Type: Application
    Filed: March 17, 2009
    Publication date: September 23, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Alan Xuguang Wang, Xiaobin Wang, Dimitar V. Dimitrov, Hai Li, Haiwen Xi, Harry Hongyue Liu
  • Publication number: 20100238712
    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
    Type: Application
    Filed: June 4, 2010
    Publication date: September 23, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li
  • Publication number: 20100232211
    Abstract: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.
    Type: Application
    Filed: May 28, 2010
    Publication date: September 16, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hongyue Liu, Yong Lu, Andrew Carter, Yiran Chen, Hai Li
  • Publication number: 20100232206
    Abstract: An apparatus and associated method for writing data to a non-volatile memory cell, such as a resistive random access memory (RRAM) cell. In some embodiments, a control circuitry is configured to write a logic state to a resistive sense element while simultaneously verifying the logic state of the resistive sense element.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 16, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hai Li, Yiran Chen, Harry Hongyue Liu, Alan Xuguang Wang
  • Publication number: 20100207219
    Abstract: A magnetic memory device includes a first electrode separated from a second electrode by a magnetic tunnel junction. The first electrode provides a write current path along a length of the first electrode. The magnetic tunnel junction includes a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation. The free magnetic layer is spaced from the first electrode a distance of less than 10 nanometers. A current passing along the write current path generates a magnetic field. The magnetic field switches the free magnetic layer magnetization orientation between a high resistance state magnetization orientation and a low resistance state magnetization orientation.
    Type: Application
    Filed: February 17, 2009
    Publication date: August 19, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Insik Jin, Hongyue Liu, Yong Lu, Xiaobin Wang
  • Publication number: 20100208513
    Abstract: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
    Type: Application
    Filed: May 5, 2010
    Publication date: August 19, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Haiwen Xi, Hongyue Liu, Michael Xuefei Tang, Antoine Khoueir, Song S. Xue
  • Publication number: 20100200856
    Abstract: A method for manufacturing E-paper array substrate and an E-paper array substrate are provided. The method for manufacturing E-paper array substrate uses two masks. Steps on a surface of the array substrate structure are eliminated, so as to facilitate a subsequent coating process of E-ink and enable a uniform distribution of a drain electric field. An E-paper array substrate is further provided.
    Type: Application
    Filed: December 1, 2009
    Publication date: August 12, 2010
    Applicant: BOE TECHNOLOGY GROUP CO., LTD
    Inventors: Wenjie HU, Zenghui SUN, Hongyu LIU, Gang WANG, Xibin SHAO