Patents by Inventor Hongyu Liu

Hongyu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7898838
    Abstract: Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit. Then the method includes adjusting the first or the second read current, read voltages, or storage device capacitance for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: March 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Henry Huang, Hongyue Liu
  • Patent number: 7898844
    Abstract: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: March 1, 2011
    Assignee: Seagate Technology, LLC
    Inventors: Xiaobin Wang, Yiran Chen, Alan Wang, Haiwen Xi, Wenzhong Zhu, Hai Li, Hongyue Liu
  • Patent number: 7894250
    Abstract: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: February 22, 2011
    Assignee: Seagate Technology LLC
    Inventors: Alan Xuguang Wang, Xiaobin Wang, Dimitar V. Dimitrov, Hai Li, Haiwen Xi, Harry Hongyue Liu
  • Publication number: 20110032749
    Abstract: Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.
    Type: Application
    Filed: October 13, 2010
    Publication date: February 10, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Harry Hongyue Liu, Haiwen Xi, Antoine Khoueir, Song Xue
  • Publication number: 20110026307
    Abstract: Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.
    Type: Application
    Filed: October 14, 2010
    Publication date: February 3, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Maroun Georges Khoury, Hongyue Liu, Brian Lee, Andrew John Gjevre Carter
  • Publication number: 20110029714
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
    Type: Application
    Filed: October 14, 2010
    Publication date: February 3, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li
  • Patent number: 7881094
    Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for generating a reference voltage for a resistive sense memory (RSM) cell, such as an STRAM cell. A dummy reference cell used to generate a reference voltage to sense a resistive state of an adjacent RSM cell. The dummy reference cell comprises a switching device, a resistive sense element (RSE) programmed to a selected resistive state, and a dummy resistor coupled to the RSE. A magnitude of the reference voltage is set in relation to the selected resistive state of the RSE and the resistance of the dummy resistor.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: February 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Harry Hongyue Liu, KangYong Kim, Henry F. Huang
  • Patent number: 7881098
    Abstract: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: February 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Hongyue Liu, Michael Xuefei Tang, Antoine Khoueir, Song S. Xue
  • Patent number: 7881095
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: February 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • Patent number: 7881104
    Abstract: Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: February 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Hongyue Liu, Zheng Gao, Insik Jin, Dimitar V. Dimitrov
  • Publication number: 20110019466
    Abstract: A method and apparatus for repairing a stuck-at defect condition in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a resistive sense element has a magnetic tunneling junction (MTJ) and a repair plane located adjacent to the resistive sense element. The repair plane injects a magnetic field in the MTJ to repair a stuck-at defect condition.
    Type: Application
    Filed: October 7, 2010
    Publication date: January 27, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Alan Xuguang Wang, Xiaobin Wang, Dimitar V. Dimitrov, Hai Li, Haiwen Xi, Harry Hongyue Liu
  • Patent number: 7876595
    Abstract: A register having a track with a first electrode is at the first end to supply a current to the track in a first direction and a second electrode at the second end to supply a current to the track in a second direction, the second direction being opposite to the first direction. A first domain wall anchor and a second domain wall anchor are positioned proximate the track between the first electrode and the second electrode. Each of the domain wall anchors has a ferromagnetic pinned layer and a barrier layer proximate the track, with the barrier layer between the track and the ferromagnetic pinned layer. The ferromagnetic layer has a magnetization orientation pinned perpendicular to the magnetization orientation of the track.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: January 25, 2011
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Dimitar V. Dimitrov, Andreas Roelofs, Xiaobin Wang, Paul E Anderson, Hongyue Liu
  • Patent number: 7876599
    Abstract: The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory cell to form a map of the resistance state resistance values for a plurality of variable resistive memory cells within a memory array. Then a column or row is selected to be a reference column or reference row based on the map of the resistance state resistance value for a plurality of variable resistive memory cells within a memory array, to minimize read operation errors, and forming a variable resistive memory cell memory array.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: January 25, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Wenzhong Zhu, Xiaobin Wang, Henry Huang, Hongyue Liu
  • Publication number: 20110007597
    Abstract: Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 13, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Dadi Setiadi, YoungPil Kim, Harry Hongyue Liu, Hyung-Kyu Lee
  • Publication number: 20110007549
    Abstract: A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element. A bit line is electrically connected to the first resistive sense memory element and the second resistive sense memory element.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 13, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xuguang Wan, Hai Li, Hongyue Liu
  • Publication number: 20110007588
    Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 13, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hai Li, Yiran Chen, Dadi Setiadi, Harry Hongyue Liu, Brian Lee
  • Publication number: 20110007548
    Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 13, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Yong Lu, Insik Jin, YoungPil Kim, Harry Hongyue Liu
  • Publication number: 20110007581
    Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 13, 2011
    Applicant: Seagate Technology LLC
    Inventors: Chulmin Jung, Insik Jin, YoungPil Kim, Yong Lu, Harry Hongyue Liu, Andrew John Carter
  • Patent number: 7859891
    Abstract: A memory array includes a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A word line is electrically coupled to a gate of the transistor. The source line is a common source line for the plurality of magnetic tunnel junctions.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: December 28, 2010
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Hongyue Liu, Xuguang Wang
  • Patent number: 7855923
    Abstract: Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: December 21, 2010
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Harry Hongyue Liu, Henry Huang, Ran Wang