Patents by Inventor Hou-Yu Chen

Hou-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9553172
    Abstract: A semiconductor device and a method of forming the same are disclosed. The method includes receiving a substrate having a fin projecting through an isolation structure over the substrate; etching a portion of the fin, resulting in a trench; forming a doped material layer on sidewalls of the trench; and growing at least one epitaxial layer in the trench. The method further includes exposing a first portion of the at least one epitaxial layer over the isolation structure; and performing an annealing process, thereby driving dopants from the doped material layer into a second portion of the at least one epitaxial layer. The first portion of the at least one epitaxial layer provides a strained channel for the semiconductor device and the second portion of the at least one epitaxial layer provides a punch-through stopper.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Publication number: 20170012128
    Abstract: In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.
    Type: Application
    Filed: August 3, 2016
    Publication date: January 12, 2017
    Inventors: Chao-Hsuing CHEN, Hou-Yu CHEN, Chie-Iuan LIN, Yuan-Shun CHAO, Kuo Lung LI
  • Patent number: 9520502
    Abstract: A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the capping layer, and forming a gate electrode on the dielectric.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: December 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Chih-Pin Tsao, Hou-Yu Chen
  • Patent number: 9515167
    Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yonag-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 9514991
    Abstract: A FinFET device and a method for fabricating a FinFET device are disclosed. An exemplary method of fabricating a FINFET device includes providing a substrate including a fin structure including a plurality of fins and shallow trench isolation (STI) features between each fin of the fin structure. A first gate structure is formed over the fin structure. First gate spacers are formed on sidewalls of the first gate structure. The first gate spacers are removed while leaving portions of the first gate spacers within corners where the fin structure and the first gate structure meet. Second gate spacers are formed on sidewalls of the first gate structure. A dielectric layer is formed over the fin structure, the first gate structure, and the second gate spacers. The first gate structure and the portions of the first gate spacers are removed, thereby exposing sidewalls of the second gate spacers.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: December 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Publication number: 20160329252
    Abstract: A structure and method for implementation of high voltage devices within multi-gate device structures includes a substrate having a fin extending therefrom and a fin-embedded isolation region. In some examples, the fin-embedded isolation region includes an STI region. In some embodiments, the fin-embedded isolation separates a first portion of the fin from a second portion of the fin. Also, in some examples, the first portion of the fin includes a channel region. In various embodiments, a source region is formed in the first portion of the fin, a drain region is formed in the second portion of the fin, and an active gate is formed over the channel region. In some examples, the active gate is disposed adjacent to the source region. In addition, a plurality of dummy gates may be formed over the fin, to provide a uniform growth environment and growth profile for source and drain region formation.
    Type: Application
    Filed: July 18, 2016
    Publication date: November 10, 2016
    Inventors: Chih-Wei Kuo, Hou-Yu Chen
  • Patent number: 9431397
    Abstract: A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 9425313
    Abstract: In a method for manufacturing a semiconductor device, a fin structure including a first semiconductor layer, an oxide layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the oxide layer is formed. An isolation insulating layer is formed so that the second semiconductor layer of the fin structure protrudes from the isolation insulating layer while the oxide layer and the first semiconductor layer are embedded in the isolation insulating layer. A third semiconductor layer is formed on the exposed second semiconductor layer so as to form a channel.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsuing Chen, Hou-Yu Chen, Chie-Iuan Lin, Yuan-Shun Chao, Kuo Lung Li
  • Publication number: 20160233319
    Abstract: A semiconductor device and a method of forming the same are disclosed. The method includes receiving a substrate having a fin projecting through an isolation structure over the substrate; etching a portion of the fin, resulting in a trench; forming a doped material layer on sidewalls of the trench; and growing at least one epitaxial layer in the trench. The method further includes exposing a first portion of the at least one epitaxial layer over the isolation structure; and performing an annealing process, thereby driving dopants from the doped material layer into a second portion of the at least one epitaxial layer. The first portion of the at least one epitaxial layer provides a strained channel for the semiconductor device and the second portion of the at least one epitaxial layer provides a punch-through stopper.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 11, 2016
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Patent number: 9397157
    Abstract: A structure and method for implementation of high voltage devices within multi-gate device structures includes a substrate having a fin extending therefrom and a fin-embedded isolation region. In some examples, the fin-embedded isolation region includes an STI region. In some embodiments, the fin-embedded isolation separates a first portion of the fin from a second portion of the fin. Also, in some examples, the first portion of the fin includes a channel region. In various embodiments, a source region is formed in the first portion of the fin, a drain region is formed in the second portion of the fin, and an active gate is formed over the channel region. In some examples, the active gate is disposed adjacent to the source region. In addition, a plurality of dummy gates may be formed over the fin, to provide a uniform growth environment and growth profile for source and drain region formation.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Kuo, Hou-Yu Chen
  • Publication number: 20160141394
    Abstract: A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.
    Type: Application
    Filed: January 26, 2016
    Publication date: May 19, 2016
    Inventors: Wen-Tai Lu, Chun-Feng Nieh, Hou-Yu Chen, Yu-Chang Lin
  • Publication number: 20160056232
    Abstract: A structure and method for implementation of high voltage devices within multi-gate device structures includes a substrate having a fin extending therefrom and a fin-embedded isolation region. In some examples, the fin-embedded isolation region includes an STI region. In some embodiments, the fin-embedded isolation separates a first portion of the fin from a second portion of the fin. Also, in some examples, the first portion of the fin includes a channel region. In various embodiments, a source region is formed in the first portion of the fin, a drain region is formed in the second portion of the fin, and an active gate is formed over the channel region. In some examples, the active gate is disposed adjacent to the source region. In addition, a plurality of dummy gates may be formed over the fin, to provide a uniform growth environment and growth profile for source and drain region formation.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 25, 2016
    Inventors: Chih-Wei Kuo, Hou-Yu Chen
  • Publication number: 20160043002
    Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.
    Type: Application
    Filed: October 19, 2015
    Publication date: February 11, 2016
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Publication number: 20160035625
    Abstract: A FinFET device and a method for fabricating a FinFET device are disclosed. An exemplary method of fabricating a FINFET device includes providing a substrate including a fin structure including a plurality of fins and shallow trench isolation (STI) features between each fin of the fin structure. A first gate structure is formed over the fin structure. First gate spacers are formed on sidewalls of the first gate structure. The first gate spacers are removed while leaving portions of the first gate spacers within corners where the fin structure and the first gate structure meet. Second gate spacers are formed on sidewalls of the first gate structure. A dielectric layer is formed over the fin structure, the first gate structure, and the second gate spacers. The first gate structure and the portions of the first gate spacers are removed, thereby exposing sidewalls of the second gate spacers.
    Type: Application
    Filed: October 13, 2015
    Publication date: February 4, 2016
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 9252271
    Abstract: A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wen-Tai Lu, Hou-Yu Chen, Yu-Chang Lin, Chun-Feng Nieh
  • Publication number: 20160013297
    Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.
    Type: Application
    Filed: September 25, 2015
    Publication date: January 14, 2016
    Inventors: Yonag-Yan Lu, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 9171925
    Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: October 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 9166044
    Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Tai Lu, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 9166053
    Abstract: A FinFET device and a method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate including a fin structure, the fin structure including a first and a second fin. The FinFET device further includes a shallow trench isolation (STI) feature disposed on the substrate and between the first and the second fins. The FinFET device further includes a gate dielectric disposed on the first and the second fins. The FinFET device further includes a gate structure disposed on the gate dielectric. The gate structure traverses the first fin, the second fin, and the STI feature between the first fin and the second fin and has a longitudinal stepped profile.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Publication number: 20150249138
    Abstract: A method of fabricating a fin field effect transistor (FinFET) includes forming a first fin and a second fin extending upward from a substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, selectively forming a bulbous epitaxial layer covering a portion of each fin, annealing the substrate to convert at least a portion of the bulbous epitaxial layer to silicide and depositing a metal layer at least in the cavity. The first fin and the second fin are adjacent. A portion of the first fin and a portion of the second fin extend beyond the top surface of the insulation layer. The bulbous epitaxial layer defines an hourglass shaped cavity between adjacent fins.
    Type: Application
    Filed: May 13, 2015
    Publication date: September 3, 2015
    Inventors: Donald Y. CHAO, Hou-Yu CHEN, Shyh-Horng YANG