Patents by Inventor Hou-Yu Chen
Hou-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9123564Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first semiconductor device. The first semiconductor device includes a first active region having a first doped region and a second doped region over the first doped region. The second doped region includes a first bottom portion and a first sidewall. The first bottom portion includes a first bottom portion inner surface, a first bottom portion outer surface, a first bottom portion height and a first bottom portion width. The first sidewall includes a first sidewall inner surface, a first sidewall outer surface, a first sidewall width and a first sidewall height, the first sidewall height greater than the first bottom portion height. A method of making a semiconductor device is also provided.Type: GrantFiled: December 5, 2013Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Chang Lin, Wen-Tai Lu, Li-Ting Wang, Chun-Feng Nieh, Hou-Yu Chen, Huicheng Chang
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Publication number: 20150162333Abstract: A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material.Type: ApplicationFiled: February 16, 2015Publication date: June 11, 2015Inventors: Chih-Wei Kuo, Yuaan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20150162330Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first semiconductor device. The first semiconductor device includes a first active region having a first doped region and a second doped region over the first doped region. The second doped region includes a first bottom portion and a first sidewall. The first bottom portion includes a first bottom portion inner surface, a first bottom portion outer surface, a first bottom portion height and a first bottom portion width. The first sidewall includes a first sidewall inner surface, a first sidewall outer surface, a first sidewall width and a first sidewall height, the first sidewall height greater than the first bottom portion height. A method of making a semiconductor device is also provided.Type: ApplicationFiled: December 5, 2013Publication date: June 11, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yu-Chang Lin, Wen-Tai Lu, Li-Ting Wang, Chun-Feng Nieh, Hou-Yu Chen, Huicheng Chang
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Patent number: 9053934Abstract: A method of fabricating a fin field effect transistor (FinFET) comprises providing a substrate comprising a major surface, forming a first and second fin extending upward from the substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, wherein a portion of the first and second fin extend beyond the top surface of the insulation layer. The method also includes selectively growing an epitaxial layer covering each fin, annealing the substrate to have each fin covered by a bulbous epitaxial layer defining an hourglass shaped cavity between adjacent fins, wherein the cavity comprises an upper and lower portion. The method includes forming a metal material over the bulbous epitaxial layer and annealing the substrate to convert the bulbous epitaxial layer bordering the lower portion of the cavity to silicide.Type: GrantFiled: January 16, 2014Date of Patent: June 9, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Donald Y. Chao, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20150145066Abstract: A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wen-Tai Lu, Hou-Yu Chen, Yu-Chang Lin, Chun-Feng Nieh
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Publication number: 20150102392Abstract: A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the capping layer, and forming a gate electrode on the dielectric.Type: ApplicationFiled: October 15, 2013Publication date: April 16, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hua Yu, Chih-Pin Tsao, Hou-Yu Chen
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Patent number: 9000536Abstract: The present disclosure relates a Fin field effect transistor (FinFET) device having large effective oxide thickness that mitigates hot carrier injection, and an associated method of formation. In some embodiments, the FinFET device has a conductive channel of a first fin protruding from a planar substrate. The conductive channel has a non-conductive highly doped region located along multiple outer edges of the channel region. A gate region protrudes from the planar substrate as a second fin that overlies the first fin. A gate dielectric region is located between the non-conductive highly doped region and the gate region. The non-conductive highly doped region and the gate dielectric region collectively provide for an effective oxide thickness of the FinFET device that allow a low electric field across gate oxide and less hot carrier injection.Type: GrantFiled: June 28, 2013Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Wei Kuo, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20150091086Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Tai Lu, Hou-Yu Chen, Shyh-Horng Yang
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Patent number: 8956931Abstract: A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material.Type: GrantFiled: February 21, 2013Date of Patent: February 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20150001593Abstract: The present disclosure relates a Fin field effect transistor (FinFET) device having large effective oxide thickness that mitigates hot carrier injection, and an associated method of formation. In some embodiments, the FinFET device has a conductive channel of a first fin protruding from a planar substrate. The conductive channel has a non-conductive highly doped region located along multiple outer edges of the channel region. A gate region protrudes from the planar substrate as a second fin that overlies the first fin. A gate dielectric region is located between the non-conductive highly doped region and the gate region. The non-conductive highly doped region and the gate dielectric region collectively provide for an effective oxide thickness of the FinFET device that allow a low electric field across gate oxide and less hot carrier injection.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Chih-Wei Kuo, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20140231924Abstract: A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material.Type: ApplicationFiled: February 21, 2013Publication date: August 21, 2014Applicant: Taiwan Semiconductor Manufacturing Company, LtdInventors: Chih-Wei Kuo, Yuaan-Shun Chao, Hou-Yu Chen, Shyh-Homg Yang
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Publication number: 20140134831Abstract: A method of fabricating a fin field effect transistor (FinFET) comprises providing a substrate comprising a major surface, forming a first and second fin extending upward from the substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, wherein a portion of the first and second fin extend beyond the top surface of the insulation layer. The method also includes selectively growing an epitaxial layer covering each fin, annealing the substrate to have each fin covered by a bulbous epitaxial layer defining an hourglass shaped cavity between adjacent fins, wherein the cavity comprises an upper and lower portion. The method includes forming a metal material over the bulbous epitaxial layer and annealing the substrate to convert the bulbous epitaxial layer bordering the lower portion of the cavity to silicide.Type: ApplicationFiled: January 16, 2014Publication date: May 15, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Donald Y. CHAO, Hou-Yu CHEN, Shyh-Horng YANG
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Patent number: 8659032Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a first fin and a second fin extending upward from the substrate major surface to a first height; an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, whereby portions of the fins extend beyond the top surface of the insulation layer; each fin covered by a bulbous epitaxial layer defining an hourglass shaped cavity between adjacent fins, the cavity comprising upper and lower portions, wherein the epitaxial layer bordering the lower portion of the cavity is converted to silicide.Type: GrantFiled: January 31, 2012Date of Patent: February 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Donald Y. Chao, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20130285141Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.Type: ApplicationFiled: April 26, 2012Publication date: October 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
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Publication number: 20130193446Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a first fin and a second fin extending upward from the substrate major surface to a first height; an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, whereby portions of the fins extend beyond the top surface of the insulation layer; each fin covered by a bulbous epitaxial layer defining an hourglass shaped cavity between adjacent fins, the cavity comprising upper and lower portions, wherein the epitaxial layer bordering the lower portion of the cavity is converted to silicide.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Donald Y. CHAO, Hou-Yu CHEN, Shyh-Horng YANG
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Patent number: 8405168Abstract: The present invention discloses a nanowire fabrication method and a semiconductor element using a nanowire fabricated thereby. The method of the present invention comprises steps: providing a substrate; sequentially depositing a silicon dioxide layer and a silicon nitride layer on the substrate; forming a patterned photoresist layer on the silicon nitride layer; using the patterned photoresist layer as a mask to etch the silicon nitride layer and the silicon dioxide layer with the substrate partly etched away to form a protrusion; removing the patterned photoresist layer to form an isolation layer; removing the silicon nitride and the silicon dioxide layer, sequentially depositing a dielectric layer and a polysilicon layer; and anisotropically etching the polysilicon layer to form nanowires on a region of the dielectric layer, which is around sidewalls of the protrusion.Type: GrantFiled: January 31, 2011Date of Patent: March 26, 2013Assignee: National Applied Research LaboratoriesInventors: Chia-Yi Lin, Min-Cheng Chen, Hou-Yu Chen
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Publication number: 20120146161Abstract: The present invention discloses a nanowire fabrication method and a semiconductor element using a nanowire fabricated thereby. The method of the present invention comprises steps: providing a substrate; sequentially depositing a silicon dioxide layer and a silicon nitride layer on the substrate; forming a patterned photoresist layer on the silicon nitride layer; using the patterned photoresist layer as a mask to etch the silicon nitride layer and the silicon dioxide layer with the substrate partly etched away to form a protrusion; removing the patterned photoresist layer to form an isolation layer; removing the silicon nitride and the silicon dioxide layer, sequentially depositing a dielectric layer and a polysilicon layer; and anisotropically etching the polysilicon layer to form nanowires on a region of the dielectric layer, which is around sidewalls of the protrusion.Type: ApplicationFiled: January 31, 2011Publication date: June 14, 2012Inventors: Chia-Yi LIN, Min-Cheng Chen, Hou-Yu Chen
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Patent number: 8048747Abstract: The present disclosure fabricates an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory device. The memory device is stacked with memory layers having a low aspect ratio. The memory device can be easily fabricated with only two extra masks for saving cost. The present disclosure uses a general method for mass-producing TFT and is thus fit for fabricating NAND-type or NOR-type flash memory to be used as embedded memory in a system-on-chip.Type: GrantFiled: November 2, 2010Date of Patent: November 1, 2011Assignee: National Applied Research LaboratoriesInventors: Min-Cheng Chen, Hou-Yu Chen, Chia-Yi Lin
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Patent number: 7943986Abstract: A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two ends of a cross bar of the T-shaped active region and a body contact region forms a leg of the T-shaped active region. A gate oxide layer is grown on the active region. A polysilicon layer is deposited overlying the gate oxide layer and patterned to form a gate, where an end of the gate partially overlies the body contact region to complete formation of a Finfet device with body contact.Type: GrantFiled: June 12, 2007Date of Patent: May 17, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Nan Yang, Yi-Lang Chen, Hou-Yu Chen, Fu-Liang Yang, Chenming Hu
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Publication number: 20070228372Abstract: A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two ends of a cross bar of the T-shaped active region and a body contact region forms a leg of the T-shaped active region. A gate oxide layer is grown on the active region. A polysilicon layer is deposited overlying the gate oxide layer and patterned to form a gate, where an end of the gate partially overlies the body contact region to complete formation of a Finfet device with body contact.Type: ApplicationFiled: June 12, 2007Publication date: October 4, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Nan Yang, Yi-Lang Chen, Hou-Yu Chen, Fu-Liang Yang, Chenming Hu