Patents by Inventor How T. Lin
How T. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8607445Abstract: A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art.Type: GrantFiled: June 14, 2012Date of Patent: December 17, 2013Assignee: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin
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Patent number: 8501575Abstract: Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.Type: GrantFiled: October 22, 2010Date of Patent: August 6, 2013Assignee: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, Frank D. Egitto, How T. Lin, John M. Lauffer, Voya R. Markovich
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Publication number: 20120260063Abstract: A detachable, logic leaf module having dendritic projections on a surface is connected to a recessed area on the surface of a cluster interface board. The projections are used for electrically connecting the logic module device to the cluster interface board or the like, the projections on the surface of the logic leaf being flexibly and conductively wired to the receiving area on the surface of the cluster interface board. The logic leaf connector is removable without the need for solder softening thermal cycles or special tools, and permits the simple removal or replacement of an individual leaf at any time.Type: ApplicationFiled: April 8, 2011Publication date: October 11, 2012Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.Inventors: Voya R. Markovich, How T. Lin, Benson Chan, Frank D. Egitto
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Publication number: 20120223047Abstract: Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.Type: ApplicationFiled: October 22, 2010Publication date: September 6, 2012Applicant: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, Frank D. Egitto, How T. Lin, John M. Lauffer, Voya R. Markovich
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Patent number: 8240031Abstract: A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal.Type: GrantFiled: July 16, 2010Date of Patent: August 14, 2012Assignee: Endicott International Technologies, Inc.Inventors: Voya R. Markovich, Ronald V. Smith, How T. Lin, Frank D. Egitto, Rabindra N. Das, William E. Wilson, Rajinder S. Rai
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Publication number: 20120015532Abstract: A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal.Type: ApplicationFiled: July 16, 2010Publication date: January 19, 2012Applicant: Endicott Interconnect Technologies, Inc.Inventors: Voya R. Markovich, Ronald V. Smith, How T. Lin, Frank D. Egitto, Rabindra N. Das, William E. Wilson, Rajinder S. Rai
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Patent number: 7897877Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.Type: GrantFiled: May 23, 2006Date of Patent: March 1, 2011Assignee: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin, Voya R. Markovich
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Patent number: 7841741Abstract: An LED lighting assembly including a plurality of individual LEDs mounted on a common, bendable heat sinking member designed to remove heat from the LEDs during operation and also to be formed (bent) to provide the desired light direction and intensity. Several such assemblies may be used within an LED lamp, as also provided herein. The lamp is ideal for use within medical and dental environments to assure optimal light onto a patient located at a specified distance from the lamp.Type: GrantFiled: April 2, 2007Date of Patent: November 30, 2010Assignee: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, John E. Kozol, John M. Lauffer, How T. Lin
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Patent number: 7803688Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.Type: GrantFiled: March 2, 2009Date of Patent: September 28, 2010Assignee: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin, Voya R. Markovich
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Patent number: 7738249Abstract: An electrical assembly which includes a circuitized substrate including a first plurality of dielectric and electrically conductive circuit layers alternatively oriented in a stacked orientation, a thermal cooling structure bonded to one of the dielectric layers and at least one electrical component mounted on the circuitized substrate. The circuitized substrate includes a plurality of electrically conductive and thermally conductive thru-holes located therein, selected ones of the thermally conductive thru-holes thermally coupled to the electrical component(s) and extending through the first plurality of dielectric and electrically conductive circuit layers and being thermally coupled to the thermal cooling structure, each of these selected ones of thermally conductive thru-holes providing a thermal path from the electrical component to the thermal cooling structure during assembly operation.Type: GrantFiled: October 25, 2007Date of Patent: June 15, 2010Assignee: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, Frank D. Egitto, How T. Lin, Roy H. Magnuson, Voya R. Markovich, David L. Thomas
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Patent number: 7713767Abstract: A method of making a circuitized substrate (e.g., PCB) including at least one and possibly several internal optical pathways as part thereof such that the resulting substrate will be capable of transmitting and/or receiving both electrical and optical signals. The method involves forming at least one opening between a side of the optical core and an adjacent upstanding member such that the opening is defined by at least one angular sidewall. Light passing through the optical core material (or into the core from above) is reflected off this angular sidewall. The medium (e.g., air) within the opening thus also serves as a reflecting medium due to its own reflective index in comparison to that of the adjacent optical core material. The method utilizes many processes used in conventional PCB manufacturing, thereby keeping costs to a minimum.Type: GrantFiled: October 9, 2007Date of Patent: May 11, 2010Assignee: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, How T. Lin, Roy H. Magnuson, Voya R. Markovich, Mark D. Poliks
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Patent number: 7629559Abstract: A method of improving conductive paste connections in a circuitized substrate in which at least one and preferably a series of high voltage pulses are applied across the paste and at least one and preferably a series of high current pulses are applied, both series of pulses applied separately. The result is an increase in the number of conductive paths through the paste connections from those present prior to the pulse applications and a corresponding resistance reduction in said connections.Type: GrantFiled: December 19, 2005Date of Patent: December 8, 2009Assignee: Endicott Interconnect Technologies, Inc.Inventors: Subahu D. Desai, John M. Lauffer, How T. Lin, Voya R. Markovich, Ronald V. Smith
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Publication number: 20090206051Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.Type: ApplicationFiled: March 2, 2009Publication date: August 20, 2009Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin, Voya R. Markovich
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Patent number: 7541058Abstract: A circuitized substrate (e.g., PCB) including an internal optical pathway as part thereof such that the substrate is capable of transmitting and/or receiving both electrical and optical signals. The substrate includes an angular reflector on one of the cladding layers such that optical signals passing through the optical core will impinge on the angled reflecting surfaces of the angular reflector and be reflected up through an opening (including one with optically transparent material therein), e.g., to a second circuitized substrate also having at least one internal optical pathway as part thereof, to thus interconnect the two substrates optically. A method of making the substrate is also provided.Type: GrantFiled: October 9, 2007Date of Patent: June 2, 2009Assignee: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, How T. Lin, Roy H. Magnuson, Voya R. Markovich, Mark D. Poliks
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Publication number: 20090109624Abstract: An electrical assembly which includes a circuitized substrate including a first plurality of dielectric and electrically conductive circuit layers alternatively oriented in a stacked orientation, a thermal cooling structure bonded to one of the dielectric layers and at least one electrical component mounted on the circuitized substrate. The circuitized substrate includes a plurality of electrically conductive and thermally conductive thru-holes located therein, selected ones of the thermally conductive thru-holes thermally coupled to the electrical component(s) and extending through the first plurality of dielectric and electrically conductive circuit layers and being thermally coupled to the thermal cooling structure, each of these selected ones of thermally conductive thru-holes providing a thermal path from the electrical component to the thermal cooling structure during assembly operation.Type: ApplicationFiled: October 25, 2007Publication date: April 30, 2009Applicant: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, Frank D. Egitto, How T. Lin, Roy H. Magnuson, Voya R. Markovich, David L. Thomas
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Publication number: 20090092353Abstract: A circuitized substrate (e.g., PCB) including an internal optical pathway as part thereof such that the substrate is capable of transmitting and/or receiving both electrical and optical signals. The substrate includes an angular reflector on one of the cladding layers such that optical signals passing through the optical core will impinge on the angled reflecting surfaces of the angular reflector and be reflected up through an opening (including one with optically transparent material therein), e.g., to a second circuitized substrate also having at least one internal optical pathway as part thereof, to thus interconnect the two substrates optically. A method of making the substrate is also provided.Type: ApplicationFiled: October 9, 2007Publication date: April 9, 2009Applicant: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, How T. Lin, Roy H. Magnuson, Voya R. Markovich, Mark D. Poliks
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Publication number: 20090093073Abstract: A method of making a circuitized substrate (e.g., PCB) including at least one and possibly several internal optical pathways as part thereof such that the resulting substrate will be capable of transmitting and/or receiving both electrical and optical signals. The method involves forming at least one opening between a side of the optical core and an adjacent upstanding member such that the opening is defined by at least one angular sidewall. Light passing through the optical core material (or into the core from above) is reflected off this angular sidewall. The medium (e.g., air) within the opening thus also serves as a reflecting medium due to its own reflective index in comparison to that of the adjacent optical core material. The method utilizes many processes used in conventional PCB manufacturing, thereby keeping costs to a minimum.Type: ApplicationFiled: October 9, 2007Publication date: April 9, 2009Applicant: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, How T. Lin, Roy H. Magnuson, Voya R. Markovich, Mark D. Poliks
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Patent number: 7511518Abstract: A method of making an interposer in which at least two dielectric layers are bonded to each other to sandwich a plurality of conductors there-between. The conductors each electrically couple a respective pair of opposed electrical contacts which are formed within and protrude from openings which are also formed within the dielectric layers as part of this method. The resulting interposer is ideally suited for use as part of a test apparatus to interconnect highly dense patterns of solder ball contacts of a semiconductor chip to lesser dense arrays of contacts on the apparatus's printed circuit board.Type: GrantFiled: September 27, 2007Date of Patent: March 31, 2009Assignee: Endicott Interconnect Technologies, Inc.Inventors: Frank D. Egitto, How T. Lin
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Patent number: 7449381Abstract: A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. The capacitive substrate may be incorporated within a larger circuitized substrate, e.g., to form an electrical assembly. A method of making an information handling system including such substrates is also provided.Type: GrantFiled: February 13, 2006Date of Patent: November 11, 2008Assignee: Endicott Interconect Technologies, Inc.Inventors: Rabindra N. Das, John M. Lauffer, How T. Lin, Voya R. Markovich
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Patent number: 7441709Abstract: An electronic card assembly is provided which includes a protective housing having a movable card therein. The card, in one example one having a magnetic stripe, has its information erased when being inserted into the housing and re-written back onto its information portion (magnetic stripe) during card withdrawal, provided appropriate human information (e.g., from a fingerprint) is received by the assembly's reader component.Type: GrantFiled: March 23, 2005Date of Patent: October 28, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, How T. Lin, Voya R. Markovich, Ronald V. Smith