Patents by Inventor How T. Lin

How T. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080248596
    Abstract: A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art.
    Type: Application
    Filed: July 26, 2007
    Publication date: October 9, 2008
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Frank D. Egitto, How T. Lin, John M. Lauffer, Voya R. Markovich
  • Publication number: 20080238323
    Abstract: An LED lighting assembly including a plurality of individual LEDs mounted on a common, bendable heat sinking member designed to remove heat from the LEDs during operation and also to be formed (bent) to provide the desired light direction and intensity. Several such assemblies may be used within an LED lamp, as also provided herein. The lamp is ideal for use within medical and dental environments to assure optimal light onto a patient located at a specified distance from the lamp.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 2, 2008
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Benson Chan, John E. Kozol, John M. Lauffer, How T. Lin
  • Patent number: 7429510
    Abstract: A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. Photoimageable material is used to facilitate positioning of the capacitive dielectric being printed. The capacitive substrate may be incorporated within a larger circuitized substrate, e.g., to form an electrical assembly. A method of making an information handling system including such substrates is also provided.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: September 30, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, John M. Lauffer, How T. Lin, Voya R. Markovich
  • Patent number: 7326643
    Abstract: A method of making circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 5, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Subahu D. Desai, How T. Lin, John M. Lauffer, Voya R. Markovich, David L. Thomas
  • Publication number: 20070275525
    Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.
    Type: Application
    Filed: May 23, 2006
    Publication date: November 29, 2007
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin, Voya R. Markovich
  • Patent number: 7292055
    Abstract: An interposer including at least two dielectric layers bonded to each other, sandwiching a plurality of conductors there-between. The conductors each electrically couple a respective pair of opposed electrical contacts formed within and protruding from openings with the dielectric layers.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: November 6, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Frank D. Egitto, How T. Lin
  • Patent number: 7253502
    Abstract: A circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device. The substrate is preferably combined with other dielectric-circuit layered assemblies to form a multilayered substrate on which can be positioned discrete electronic components (e.g., a logic chip) coupled to the internal memory device to work in combination therewith. An electrical assembly capable of using the substrate is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: August 7, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Subahu D. Desai, How T. Lin, John M. Lauffer, Voya R. Markovich, David L. Thomas
  • Patent number: 7152319
    Abstract: A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: December 26, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Benson Chan, John M. Lauffer, How T. Lin, Voya R. Markovich, David L. Thomas
  • Patent number: 7130522
    Abstract: A method is provided for making ferrules for connecting optical fibers to other optical fibers or to an optical input device such as an optical chip. The method utilizes ceramic greensheets or silicon wafers. In one method, the greensheets are stacked and laminated and then fiber optic through openings are provided in the laminate for holding the fibers. The laminate is then sintered forming the ferrule.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: October 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: John U Knickerbocker, How T Lin
  • Patent number: 7108809
    Abstract: An optical coupler arrangement which is employed for replicating surface features of diverse types of optical devices. Also disclosed is to a novel method of accurately replicating surface features of optical devices; particularly through the utilization of the novel optical coupler arrangement.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: September 19, 2006
    Assignee: International Business Machines Corporation
    Inventors: Benson Chan, Richard R. Hall, How T. Lin, Christopher J. Majka, John H. Sherman
  • Patent number: 7045897
    Abstract: An electrical assembly which includes a circuitized substrate comprised of an organic dielectric material having a first electrically conductive pattern thereon. At least part of the dielectric layer and pattern form the first, base portion of an organic memory device, the remaining portion being a second, polymer layer formed over the part of the pattern and a second conductive circuit formed on the polymer layer. A second dielectric layer if formed over the second conductive circuit and first circuit pattern to enclose the organic memory device. The device is electrically coupled to a first electrical component through the second dielectric layer and this first electrical component is electrically coupled to a second electrical component. A method of making the electrical assembly is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: May 16, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Frank D. Egitto, John M. Lauffer, How T. Lin, Voya R. Markovich, David L. Thomas
  • Patent number: 6982387
    Abstract: A method and associated structure for forming a conductive path within a laminate. A conductive element is presses into an opening in the laminate such that portion of at least one end of the conductive element extends beyond a surface of the laminate. A compressive pressure is applied to the portion of the at least one end of the conductive element. The compressive pressure applied to the at least one end of the conductive element forms a contact pad extending beyond the surface of the laminate. The conductive element may include an inner element covered by an outer element.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: January 3, 2006
    Assignee: International Business Machines Corporation
    Inventors: Richard R. Hall, How T. Lin, Christopher J. Majka, Matthew F. Seward, Ronald V. Smith
  • Patent number: 6827505
    Abstract: An optical-electronic package for an electronic device provides electrical connections to the electronic device and optical fiber connections to the electronic device. The package includes a high thermal conductivity base which has a pedestal to support and provide heat transfer connection to the electronic device. A seal band is formed on the base and a casing is bonded to the seal band. The casing has side feedthroughs for the electrical connections from the electronic device, and the casing has top feedthroughs or grooves for the optical fiber connections from the electronic device. A lid is hermetically sealed to the top of the casing. The lid has retractable means for forming a bend in the optical fibers to provide strain relief when the lid is placed on the casing. The retractable means for forming a bend in the optical fibers is retractable once the lid is sealed on the casing.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: December 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Subhash L. Shinde, L. Wynn Herron, Mario J. Interrante, How T. Lin, Steven P. Ostrander, Sudipta K. Ray, William E. Sablinski, Hilton Toy
  • Patent number: 6828514
    Abstract: A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: December 7, 2004
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Benson Chan, John M. Lauffer, How T. Lin, Voya R. Markovich, David L. Thomas
  • Publication number: 20040231888
    Abstract: A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.
    Type: Application
    Filed: March 30, 2004
    Publication date: November 25, 2004
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Benson Chan, John M. Lauffer, How T. Lin, Voya R. Markovich, David L. Thomas
  • Publication number: 20040150969
    Abstract: A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.
    Type: Application
    Filed: January 30, 2003
    Publication date: August 5, 2004
    Applicant: Endicott Interconnect Technologies Inc.
    Inventors: Benson Chan, John M. Lauffer, How T. Lin, Voya R. Markovich, David L. Thomas
  • Publication number: 20040114884
    Abstract: An optical-electronic package for an electronic device provides electrical connections to the electronic device and optical fiber connections to the electronic device. The package includes a high thermal conductivity base which has a pedestal to support and provide heat transfer connection to the electronic device. A seal band is formed on the base and a casing is bonded to the seal band. The casing has side feedthroughs for the electrical connections from the electronic device, and the casing has top feedthroughs or grooves for the optical fiber connections from the electronic device. A lid is hermetically sealed to the top of the casing. The lid has retractable means for forming a bend in the optical fibers to provide strain relief when the lid is placed on the casing. The retractable means for forming a bend in the optical fibers is retractable once the lid is sealed on the casing.
    Type: Application
    Filed: December 16, 2002
    Publication date: June 17, 2004
    Applicant: International Business Machines Corporation
    Inventors: Subhash L. Shinde, L. Wynn Herron, Mario J. Interrante, How T. Lin, Steven P. Ostrander, Sudipta K. Ray, William E. Sablinski, Hilton Toy
  • Publication number: 20040061248
    Abstract: An optical coupler arrangement which is employed for replicating surface features of diverse types of optical devices. Also disclosed is to a novel method of accurately replicating surface features of optical devices; particularly through the utilization of the novel optical coupler arrangement.
    Type: Application
    Filed: October 1, 2002
    Publication date: April 1, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benson Chan, Richard R. Hall, How T. Lin, Christopher J. Majka, John H. Sherman
  • Patent number: 6712261
    Abstract: An arrangement and method for the insertion the leading end of a length of a metallic element into a through hole which is formed in a substrate, and for heat deforming the inserted leading portion of the metallic element into a predetermined configuration prior to severing therefrom the remaining length of the metallic element.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: March 30, 2004
    Assignee: International Business Machines Corporation
    Inventors: Richard R. Hall, How T. Lin, Christopher J. Majka, Matthew F. Seward, Ronald V. Smith
  • Patent number: 6651013
    Abstract: A method and apparatus for locating a short between two nets in an electrical wire network of a microelectronic structure (e.g., chip, chip carrier, circuit card, etc.). A first net and a second net of the electrical wire are electrically shorted at an unknown point PS on the first net. Points PA and PB on the first net such are selected such that PS is located on a path between PA and PB along the first net. A constant current pulse source is electrically connected between PA and PB and is activated. Voltage drops VAB (from PA to PB) and VAC (from PA to a point PC on the second net) are measured. A length LAS of the path from PA to PS is calculated as a function of VAC/VAB. Computer graphics may be used to graphically display the location of the short within the microelectronic structure.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: November 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: How T. Lin, Christopher J. Majka, Matthew Francis Seward