Patents by Inventor Howard Wang

Howard Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11483175
    Abstract: Virtualization software that includes a VDRB (virtual distributed router/bridge) module for performing L3 routing and/or bridging operations is provided. At least some of the VDRBs are configured as VDBs (virtual distributed bridge) for performing bridging operations between different network segments in a distributed manner. The bridging tasks of a network are partitioned among several VDBs of the network based on MAC addresses. MAC addresses of VMs or other types of network nodes belonging to an overlay logical network are partitioned into several shards, each shard of MAC addresses assigned to a VDB in the network. Each VDB assigned a shard of MAC addresses performs bridging when it receives a packet bearing a MAC address belonging to its assigned shard. A VDB does not perform bridging on packets that do not have MAC address that falls within the VDB's shard of MAC addresses.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: October 25, 2022
    Assignee: NICIRA, INC.
    Inventors: Rahul Korivi Subramaniyam, Howard Wang, Ganesan Chandrashekhar, Vivek Agarwal, Ram Dular Singh
  • Publication number: 20220078110
    Abstract: A logical routing element (LRE) having multiple designated instances for routing packets from physical hosts (PH) to a logical network is provided. A PH in a network segment with multiple designated instances can choose among the multiple designated instances for sending network traffic to other network nodes in the logical network according to a load balancing algorithm. Each logical interface (LIF) of an LRE is defined to be addressable by multiple identifiers or addresses, and each LIF identifier or address is assigned to a different designated instance.
    Type: Application
    Filed: November 12, 2021
    Publication date: March 10, 2022
    Inventors: Vivek Agarwal, Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Ram Dular Singh, Howard Wang
  • Patent number: 11190443
    Abstract: A logical routing element (LRE) having multiple designated instances for routing packets from physical hosts (PH) to a logical network is provided. A PH in a network segment with multiple designated instances can choose among the multiple designated instances for sending network traffic to other network nodes in the logical network according to a load balancing algorithm. Each logical interface (LIF) of an LRE is defined to be addressable by multiple identifiers or addresses, and each LIF identifier or address is assigned to a different designated instance.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: November 30, 2021
    Assignee: NICIRA, INC.
    Inventors: Vivek Agarwal, Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Ram Dular Singh, Howard Wang
  • Patent number: 11157108
    Abstract: An exemplary touch-sensitive array for optimized edge detection includes a first electrode structure having opposing first and second ends and including: a first transmit (TX) electrode pair at the first end of the first electrode structure, a plurality of core TX electrodes disposed between the first and second ends of the first electrode structure, and a second TX electrode pair at the second end of the first electrode structure. The touch-sensitive array further includes a second electrode structure having opposing first and second ends and including: a first receive (RX) electrode pair at the first end of the second electrode structure and including a first plurality of connection members, a plurality of core RX electrodes disposed between the first and second ends of the second electrode structure, and a second RX electrode pair at the second end of the second electrode structure and including a second plurality of connection members.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: October 26, 2021
    Assignee: PARADE TECHNOLOGIES, LTD.
    Inventors: Howard Wang, Leeson Li
  • Publication number: 20210328921
    Abstract: A LRE (logical routing element) that have LIFs that are active in all host machines spanned by the LRE as well as LIFs that are active in only a subset of those spanned host machines is provided. A host machine having an active LIF for a particular L2 segment would perform the L3 routing operations for network traffic related to that L2 segment. A host machine having an inactive LIF for the particular L2 segment would not perform L3 routing operations for the network traffic of the L2 segment.
    Type: Application
    Filed: June 28, 2021
    Publication date: October 21, 2021
    Inventors: Vivek Agarwal, Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Howard Wang, Ram Dular Singh
  • Publication number: 20210294622
    Abstract: Some embodiments provide a method of operating several logical networks over a network virtualization infrastructure. The method defines a managed physical switching element (MPSE) that includes several ports for forwarding packets to and from a plurality of virtual machines. Each port is associated with a unique media access control (MAC) address. The metho defines several managed physical routing elements (MPREs) for the several different logical networks. Each MPRE is for receiving data packets from a same port of the MPSE. Each MPRE is defined for a different logical network and for routing data packets between different segments of the logical network. The method provides the defined MPSE and the defined plurality of MPREs to a plurality of host machines as configuration data.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Ram Dular Singh, Vivek Agarwal, Howard Wang
  • Patent number: 11050666
    Abstract: A LRE (logical routing element) that have LIFs that are active in all host machines spanned by the LRE as well as LIFs that are active in only a subset of those spanned host machines is provided. A host machine having an active LIF for a particular L2 segment would perform the L3 routing operations for network traffic related to that L2 segment. A host machine having an inactive LIF for the particular L2 segment would not perform L3 routing operations for the network traffic of the L2 segment.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: June 29, 2021
    Assignee: NICIRA, INC.
    Inventors: Vivek Agarwal, Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Howard Wang, Ram Dular Singh
  • Patent number: 11045740
    Abstract: A magnetic block track provided as a set has track blocks provided as a set of track blocks selected from at least one of the following of the group of: basic blocks; straight road section blocks; and curved section blocks. The track blocks are generally planar with a top side, a bottom side, and a sidewall with a sidewall height that is less than a length of the track blocks. A pair of permanent magnets is mounted within sidewalls of the track blocks. The pair of permanent magnets are aligned to attract to each other. A first slot is formed on the track blocks starting at slot funnel formed on the sidewall. The first slot is formed between the pair of permanent magnets. A toy vehicle has a pair of protruding vehicle guides configured to engage the first slot.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: June 29, 2021
    Inventor: Howard Wang
  • Patent number: 11029982
    Abstract: Some embodiments provide a method of operating several logical networks over a network virtualization infrastructure. The method defines a managed physical switching element (MPSE) that includes several ports for forwarding packets to and from a plurality of virtual machines. Each port is associated with a unique media access control (MAC) address. The method defines several managed physical routing elements (MPREs) for the several different logical networks. Each MPRE is for receiving data packets from a same port of the MPSE. Each MPRE is defined for a different logical network and for routing data packets between different segments of the logical network. The method provides the defined MPSE and the defined plurality of MPREs to a plurality of host machines as configuration data.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: June 8, 2021
    Assignee: NICIRA, INC.
    Inventors: Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Ram Dular Singh, Vivek Agarwal, Howard Wang
  • Patent number: D928239
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: August 17, 2021
    Inventor: Howard Wang
  • Patent number: D929505
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: August 31, 2021
    Inventor: Howard Wang
  • Patent number: D930085
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: September 7, 2021
    Inventor: Howard Wang
  • Patent number: D930758
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: September 14, 2021
    Inventor: Howard Wang
  • Patent number: D933136
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: October 12, 2021
    Inventor: Howard Wang
  • Patent number: D936153
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: November 16, 2021
    Inventor: Howard Wang
  • Patent number: D936154
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: November 16, 2021
    Inventor: Howard Wang
  • Patent number: D936155
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: November 16, 2021
    Inventor: Howard Wang
  • Patent number: D961006
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: August 16, 2022
    Inventor: Howard Wang
  • Patent number: D962354
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: August 30, 2022
    Inventor: Howard Wang
  • Patent number: D968523
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 1, 2022
    Inventor: Howard Wang