Patents by Inventor Howard Wang

Howard Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210121788
    Abstract: A magnetic block track provided as a set has track blocks provided as a set of track blocks selected from at least one of the following of the group of: basic blocks; straight road section blocks; and curved section blocks. The track blocks are generally planar with a top side, a bottom side, and a sidewall with a sidewall height that is less than a length of the track blocks. A pair of permanent magnets is mounted within sidewalls of the track blocks. The pair of permanent magnets are aligned to attract to each other. A first slot is formed on the track blocks starting at slot funnel formed on the sidewall. The first slot is formed between the pair of permanent magnets. A toy vehicle has a pair of protruding vehicle guides configured to engage the first slot.
    Type: Application
    Filed: January 4, 2021
    Publication date: April 29, 2021
    Inventor: Howard WANG
  • Publication number: 20200360827
    Abstract: A magnetic block track provided as a set has track blocks provided as a set of track blocks selected from at least one of the following of the group of: basic blocks; straight road section blocks; and curved section blocks. The track blocks are generally planar with a top side, a bottom side, and a sidewall with a sidewall height that is less than a length of the track blocks. A pair of permanent magnets is mounted within sidewalls of the track blocks. The pair of permanent magnets are aligned to attract to each other. A first slot is formed on the track blocks starting at slot funnel formed on the sidewall. The first slot is formed between the pair of permanent magnets. A toy vehicle has a pair of protruding vehicle guides configured to engage the first slot.
    Type: Application
    Filed: March 23, 2020
    Publication date: November 19, 2020
    Inventor: Howard Wang
  • Publication number: 20200296038
    Abstract: A LRE (logical routing element) that have LIFs that are active in all host machines spanned by the LRE as well as LIFs that are active in only a subset of those spanned host machines is provided. A host machine having an active LIF for a particular L2 segment would perform the L3 routing operations for network traffic related to that L2 segment. A host machine having an inactive LIF for the particular L2 segment would not perform L3 routing operations for the network traffic of the L2 segment.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Vivek Agarwal, Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Howard Wang, Ram Dular Singh
  • Patent number: 10693783
    Abstract: A LRE (logical routing element) that have LIFs that are active in all host machines spanned by the LRE as well as LIFs that are active in only a subset of those spanned host machines is provided. A host machine having an active LIF for a particular L2 segment would perform the L3 routing operations for network traffic related to that L2 segment. A host machine having an inactive LIF for the particular L2 segment would not perform L3 routing operations for the network traffic of the L2 segment.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: June 23, 2020
    Assignee: NICIRA, INC.
    Inventors: Vivek Agarwal, Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Howard Wang, Ram Dular Singh
  • Publication number: 20200081728
    Abstract: Some embodiments provide a method of operating several logical networks over a network virtualization infrastructure. The method defines a managed physical switching element (MPSE) that includes several ports for forwarding packets to and from a plurality of virtual machines. Each port is associated with a unique media access control (MAC) address. The method defines several managed physical routing elements (MPREs) for the several different logical networks. Each MPRE is for receiving data packets from a same port of the MPSE. Each MPRE is defined for a different logical network and for routing data packets between different segments of the logical network. The method provides the defined MPSE and the defined plurality of MPREs to a plurality of host machines as configuration data.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 12, 2020
    Inventors: Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Ram Dular Singh, Vivek Agarwal, Howard Wang
  • Publication number: 20200067730
    Abstract: Virtualization software that includes a VDRB (virtual distributed router/bridge) module for performing L3 routing and/or bridging operations is provided. At least some of the VDRBs are configured as VDBs (virtual distributed bridge) for performing bridging operations between different network segments in a distributed manner. The bridging tasks of a network are partitioned among several VDBs of the network based on MAC addresses. MAC addresses of VMs or other types of network nodes belonging to an overlay logical network are partitioned into several shards, each shard of MAC addresses assigned to a VDB in the network. Each VDB assigned a shard of MAC addresses performs bridging when it receives a packet bearing a MAC address belonging to its assigned shard. A VDB does not perform bridging on packets that do not have MAC address that falls within the VDB's shard of MAC addresses.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Rahul Korivi Subramaniyam, Howard Wang, Ganesan Chandrashekhar, Vivek Agarwal, Ram Dular Singh
  • Patent number: 10528373
    Abstract: Some embodiments provide a method of operating several logical networks over a network virtualization infrastructure. The method defines a managed physical switching element (MPSE) that includes several ports for forwarding packets to and from a plurality of virtual machines. Each port is associated with a unique media access control (MAC) address. The metho defines several managed physical routing elements (MPREs) for the several different logical networks. Each MPRE is for receiving data packets from a same port of the MPSE. Each MPRE is defined for a different logical network and for routing data packets between different segments of the logical network. The method provides the defined MPSE and the defined plurality of MPREs to a plurality of host machines as configuration data.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 7, 2020
    Assignee: NICIRA, INC.
    Inventors: Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Ram Dular Singh, Vivek Agarwal, Howard Wang
  • Patent number: 10511458
    Abstract: Virtualization software that includes a VDRB (virtual distributed router/bridge) module for performing L3 routing and/or bridging operations is provided. At least some of the VDRBs are configured as VDBs (virtual distributed bridge) for performing bridging operations between different network segments in a distributed manner. The bridging tasks of a network are partitioned among several VDBs of the network based on MAC addresses. MAC addresses of VMs or other types of network nodes belonging to an overlay logical network are partitioned into several shards, each shard of MAC addresses assigned to a VDB in the network. Each VDB assigned a shard of MAC addresses performs bridging when it receives a packet bearing a MAC address belonging to its assigned shard. A VDB does not perform bridging on packets that do not have MAC address that falls within the VDB's shard of MAC addresses.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: December 17, 2019
    Assignee: NICIRA, INC.
    Inventors: Rahul Korivi Subramaniyam, Howard Wang, Ganesan Chandrashekhar, Vivek Agarwal, Ram Dular Singh
  • Publication number: 20190280972
    Abstract: A LRE (logical routing element) that have LIFs that are active in all host machines spanned by the LRE as well as LIFs that are active in only a subset of those spanned host machines is provided. A host machine having an active LIF for a particular L2 segment would perform the L3 routing operations for network traffic related to that L2 segment. A host machine having an inactive LIF for the particular L2 segment would not perform L3 routing operations for the network traffic of the L2 segment.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Inventors: Vivek Agarwal, Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Howard Wang, Ram Dular Singh
  • Patent number: 10361952
    Abstract: A LRE (logical routing element) that have LIFs that are active in all host machines spanned by the LRE as well as LIFs that are active in only a subset of those spanned host machines is provided. A host machine having an active LIF for a particular L2 segment would perform the L3 routing operations for network traffic related to that L2 segment. A host machine having an inactive LIF for the particular L2 segment would not perform L3 routing operations for the network traffic of the L2 segment.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 23, 2019
    Assignee: NICIRA, INC.
    Inventors: Vivek Agarwal, Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Howard Wang, Ram Dular Singh
  • Patent number: 10348625
    Abstract: A LRE (logical routing element) that have LIFs that are active in all host machines spanned by the LRE as well as LIFs that are active in only a subset of those spanned host machines is provided. A host machine having an active LIF for a particular L2 segment would perform the L3 routing operations for network traffic related to that L2 segment. A host machine having an inactive LIF for the particular L2 segment would not perform L3 routing operations for the network traffic of the L2 segment.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 9, 2019
    Assignee: NICIRA, INC.
    Inventors: Vivek Agarwal, Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Howard Wang, Ram Dular Singh
  • Publication number: 20190138236
    Abstract: A non-volatile dual inline memory module (NVDIMM) includes a registered dynamic random access memory (RDRAM) having a first capacity, and a non-volatile random access memory (NVRAM) having a second capacity. The first capacity is substantially equal to the second capacity. The NVRAM is configured with a reserved memory portion at a top of a DIMM physical address space of the NVDIMM. The reserved portion includes a label storage area for establishing a plurality of namespaces on the NVRAM.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: Price Tsai, Howard Wang, Ching-Lung Chao
  • Publication number: 20190073054
    Abstract: An exemplary touch-sensitive array for optimized edge detection includes a first electrode structure having opposing first and second ends and including: a first transmit (TX) electrode pair at the first end of the first electrode structure, a plurality of core TX electrodes disposed between the first and second ends of the first electrode structure, and a second TX electrode pair at the second end of the first electrode structure. The touch-sensitive array further includes a second electrode structure having opposing first and second ends and including: a first receive (RX) electrode pair at the first end of the second electrode structure and including a first plurality of connection members, a plurality of core RX electrodes disposed between the first and second ends of the second electrode structure, and a second RX electrode pair at the second end of the second electrode structure and including a second plurality of connection members.
    Type: Application
    Filed: August 9, 2018
    Publication date: March 7, 2019
    Inventors: Howard Wang, Leeson Li
  • Patent number: 10225184
    Abstract: A LRE (logical routing element) that have LIFs that are active in all host machines spanned by the LRE as well as LIFs that are active in only a subset of those spanned host machines is provided. A host machine having an active LIF for a particular L2 segment would perform the L3 routing operations for network traffic related to that L2 segment. A host machine having an inactive LIF for the particular L2 segment would not perform L3 routing operations for the network traffic of the L2 segment.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 5, 2019
    Assignee: NICIRA, INC.
    Inventors: Vivek Agarwal, Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Howard Wang, Ram Dular Singh
  • Publication number: 20180276013
    Abstract: Some embodiments provide a method of operating several logical networks over a network virtualization infrastructure. The method defines a managed physical switching element (MPSE) that includes several ports for forwarding packets to and from a plurality of virtual machines. Each port is associated with a unique media access control (MAC) address. The metho defines several managed physical routing elements (MPREs) for the several different logical networks. Each MPRE is for receiving data packets from a same port of the MPSE. Each MPRE is defined for a different logical network and for routing data packets between different segments of the logical network. The method provides the defined MPSE and the defined plurality of MPREs to a plurality of host machines as configuration data.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 27, 2018
    Inventors: Ganesan Chandrashekhar, Rahul Korivi Subramaniyam, Ram Dular Singh, Vivek Agarwal, Howard Wang
  • Patent number: D830475
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 9, 2018
    Inventor: Howard Wang
  • Patent number: D831129
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 16, 2018
    Inventor: Howard Wang
  • Patent number: D915528
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: April 6, 2021
    Inventor: Howard Wang
  • Patent number: D917631
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 27, 2021
    Inventor: Howard Wang
  • Patent number: D918313
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: May 4, 2021
    Inventor: Howard Wang