Patents by Inventor Howe Yin Loo

Howe Yin Loo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147654
    Abstract: The present disclosure is directed to a laptop arrangement including: a chassis defining a space that is divided into a first compartment and a second compartment, the first compartment including an air inlet and the second compartment including an air outlet; and a partitioning element positioned between the first and second compartments, whereby the partitioning element at least partially seals the first compartment from the second compartment and enables the second compartment to have a greater pressurization than the first compartment.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: Jiunn Shyong CHEE, Howe Yin LOO, Tin Poay CHUAH, Chin Kung GOH, Yew San LIM
  • Publication number: 20240006786
    Abstract: The present disclosure is directed to a printed circuit board having a composite upper surface with a first section of a first-type of printed circuit board and a second section of a second-type of printed circuit board, for which the first section of the first-type of printed circuit board and the second section of the second-type of printed circuit board are coupled, respectively, to at least one device that is configured to abridge the first and second sections of the composite upper surface. In an aspect, the second-type of printed circuit board is configured to be embedded in the first-type of printed circuit board and the first-type of printed circuit board is configured to receive the second-type of printed circuit board.
    Type: Application
    Filed: July 4, 2022
    Publication date: January 4, 2024
    Inventors: Howe Yin LOO, Tin Poay CHUAH, Jenny Shio Yin ONG, Chee Min LOH, Bok Eng CHEAH, Jackson Chung Peng KONG, Seok Ling LIM, Kooi Chi OOI
  • Publication number: 20230409084
    Abstract: A computing device includes a flexible display screen, a housing to house at least one processor device and at least one memory element, and a first wing to support a side portion of the display screen. The front face of the housing includes a center portion of the display screen. The first wing is connected to the housing by a hinge, the first wing configured to swivel about an axis defined by the hinge. The hinge is configured to lock the first wing in at least two wing positions, a first of the wing positions supports the side portion of the display screen in a first orientation, a second of the wing positions supports the side portion of the display screen in a second orientation, and the side portion of the display screen is active in the first orientation and hidden in the second orientation.
    Type: Application
    Filed: August 30, 2023
    Publication date: December 21, 2023
    Applicant: Intel Corporation
    Inventors: Chee Chun Yee, David W. Browning, Bok Eng Cheah, Jackson Chung Peng Kong, Min Suet Lim, Howe Yin Loo, Poh Tat Oh
  • Patent number: 11639623
    Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: May 2, 2023
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Howe Yin Loo, Min Suet Lim, Jackson Chung Peng Kong, Poh Tat Oh
  • Patent number: 11355427
    Abstract: Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Howe Yin Loo, Sujit Sharan, Tin Poay Chuah, Ananth Prabhakumar
  • Publication number: 20210333848
    Abstract: According to the present disclosure, a laptop may be provided with a compartment including a moveable segment, an expandable heat exchanger with a movable section, and an expandable fan unit. The release of the movable segment of the compartment from a lower portion of the compartment produces an opening in the compartment and the movable section of the expandable heat exchanger is extended downward, and the expandable fan unit is lowered when the movable segment of the compartment is released.
    Type: Application
    Filed: July 7, 2021
    Publication date: October 28, 2021
    Inventors: Jeff KU, Tin Poay CHUAH, Howe Yin LOO, Chin Kung GOH, Yew San LIM, Cora Shih Wei NIEN
  • Patent number: 11006514
    Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer mounted on a motherboard. The semiconductor package also includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package has one or more capacitors mounted on an electrical shield. The electrical shield may be embedded in the HiMB of the motherboard. Accordingly, the semiconductor package has capacitors vertically embedded between the electrical shield and the HiMB of the motherboard. The semiconductor package may also have one or more HiMB sidewalls formed on the HiMB, where each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs) with an exposed layer. The PTHs may be electrically coupled to the capacitors as the capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls (i.e., three-dimensional (3D) capacitors).
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Jia Yan Go, Min Suet Lim, Tin Poay Chuah, Seok Ling Lim, Howe Yin Loo
  • Patent number: 10943792
    Abstract: A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Min Suet Lim, Jackson Chung Peng Kong, Howe Yin Loo
  • Publication number: 20200325711
    Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 15, 2020
    Inventors: Bok Eng Cheah, Howe Yin Loo, Min Suet Lim, Jackson Chung Peng Kong, Poh Tat Oh
  • Publication number: 20200192432
    Abstract: A computing device includes a flexible display screen, a housing to house at least one processor device and at least one memory element, and a first wing to support a side portion of the display screen. The front face of the housing includes a center portion of the display screen. The first wing is connected to the housing by a hinge, the first wing configured to swivel about an axis defined by the hinge. The hinge is configured to lock the first wing in at least two wing positions, a first of the wing positions supports the side portion of the display screen in a first orientation, a second of the wing positions supports the side portion of the display screen in a second orientation, and the side portion of the display screen is active in the first orientation and hidden in the second orientation.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 18, 2020
    Applicant: Intel Corporation
    Inventors: Chee Chun Yee, David W. Browning, Bok Eng Cheah, Jackson Chung Peng Kong, Min Suet Lim, Howe Yin Loo, Poh Tat Oh
  • Patent number: 10643983
    Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having a stiffener that extends beyond a package substrate outer edge, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a package substrate having a first side, a second side opposite the first side, and an outer edge extending between the first side and the second side; an IC die coupled with the first side of the package substrate, where the IC die includes a power terminal; a stiffener coupled with the first side of the package substrate, where the stiffener surrounds the IC die and includes a conductive routing region coupled with the IC die power terminal, and a passive electronic device coupled with the conductive routing region. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Bok Eng Cheah, Jackson Chung Peng Kong, Min Suet Lim, Khang Choong Yong, Howe Yin Loo
  • Patent number: 10633898
    Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Howe Yin Loo, Min Suet Lim, Jackson Chung Peng Kong, Poh Tat Oh
  • Publication number: 20190394871
    Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer mounted on a motherboard. The semiconductor package also includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package has one or more capacitors mounted on an electrical shield. The electrical shield may be embedded in the HiMB of the motherboard. Accordingly, the semiconductor package has capacitors vertically embedded between the electrical shield and the HiMB of the motherboard. The semiconductor package may also have one or more HiMB sidewalls formed on the HiMB, where each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs) with an exposed layer. The PTHs may be electrically coupled to the capacitors as the capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls (i.e., three-dimensional (3D) capacitors).
    Type: Application
    Filed: March 30, 2017
    Publication date: December 26, 2019
    Inventors: Jia Yan GO, Min Suet LIM, Tin Poay CHUAH, Seok Ling LIM, Howe Yin LOO
  • Patent number: 10503211
    Abstract: A computing device includes a flexible display screen, a housing to house at least one processor device and at least one memory element, and a first wing to support a side portion of the display screen. The front face of the housing includes a center portion of the display screen. The first wing is connected to the housing by a hinge, the first wing configured to swivel about an axis defined by the hinge. The hinge is configured to lock the first wing in at least two wing positions, a first of the wing positions supports the side portion of the display screen in a first orientation, a second of the wing positions supports the side portion of the display screen in a second orientation, and the side portion of the display screen is active in the first orientation and hidden in the second orientation.
    Type: Grant
    Filed: September 13, 2015
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Chee Chun Yee, David W. Browning, Bok Eng Cheah, Jackson Chung Peng Kong, Min Suet Lim, Howe Yin Loo, Poh Tat Oh
  • Patent number: 10394280
    Abstract: Embodiments of wearable electronic devices, components thereof, and related systems and techniques are disclosed herein. For example, a wearable electronic device may include a wearable support structure having a first surface and a second surface; a first electrode located at the first surface, wherein, when the wearable electronic device is worn by a user on a portion of the user's body, the first electrode is arranged to contact the user's skin in the portion of the user's body; a second electrode located at the second surface, wherein, when the wearable electronic device is worn by a user on the portion of the user's body, the second electrode is arranged to not contact the user's skin in the portion of the user's body; and a resistance switch having first and second input terminals coupled to the first and second electrodes, respectively. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 27, 2019
    Assignee: INTEL CORPORATION
    Inventors: Thorsten Meyer, Dirk Plenkers, Hans-Joachim Barth, Bernd Waidhas, Yen Hsiang Chew, Kooi Chi Ooi, Howe Yin Loo
  • Publication number: 20190206698
    Abstract: A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.
    Type: Application
    Filed: September 27, 2016
    Publication date: July 4, 2019
    Inventors: Bok Eng Cheah, Min Suet Lim, Jackson Chung Peng Kong, Howe Yin Loo
  • Publication number: 20190131227
    Abstract: Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.
    Type: Application
    Filed: July 1, 2016
    Publication date: May 2, 2019
    Inventors: Howe Yin LOO, Sujit SHARAN, Tin Poay CHUAH, Ananth PRABHAKUMAR
  • Publication number: 20190093402
    Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.
    Type: Application
    Filed: June 19, 2018
    Publication date: March 28, 2019
    Inventors: Bok Eng Cheah, Howe Yin Loo, Min Suet Lim, Jackson Chung Peng Kong, Poh Tat Oh
  • Publication number: 20190013303
    Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having a stiffener that extends beyond a package substrate outer edge, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a package substrate having a first side, a second side opposite the first side, and an outer edge extending between the first side and the second side; an IC die coupled with the first side of the package substrate, where the IC die includes a power terminal; a stiffener coupled with the first side of the package substrate, where the stiffener surrounds the IC die and includes a conductive routing region coupled with the IC die power terminal, and a passive electronic device coupled with the conductive routing region. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 1, 2018
    Publication date: January 10, 2019
    Inventors: Eng Huat GOH, Bok Eng CHEAH, Jackson Chung Peng KONG, Min Suet LIM, Khang Choong YONG, Howe Yin LOO
  • Patent number: 10153253
    Abstract: A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a through-mold via package bottom interposer disposed on the package substrate on a land side. A land side board mates with the through-mold via package bottom interposer, and enough vertical space is created by the through-mold via package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Howe Yin Loo, Eng Huat Goh, Min Suet Lim, Bok Eng Cheah, Jackson Chung Peng Kong, Khang Choong Yong