Abstract: A method and system for guided power grid augmentation determines a minimum resistance path for cells within an integrated circuit (IC) design. The minimum resistance path traces a conducting wire connecting a pin of a cell to an IC tap within the IC design. A voltage drop value for each of the cells is determined so as to identify target cells having a voltage drop value that satisfies a voltage drop criteria. Polygons have defined size characteristics are defined around the minimum resistance paths of the target cells, and conductors, such as additional conductors, are generated within the defined polygons.

Abstract: An air valve comprises a casing, a valve body driving assembly and a valve body. The casing comprises a chamber, a vent hole, and at least one switching hole communicating with the chamber. The valve body driving assembly is disposed in the chamber, and comprises a pusher, a shape memory metal wire in a linkage relationship with the pusher, and two conductive members disposed in the casing and located at two ends of the shape memory metal wire respectively, the pusher travels a uniaxial displacement stroke due to a temporary change of the shape memory metal wire. The valve body is disposed in the chamber and faces the switching hole, when the pusher travels the uniaxial displacement stroke, the valve body is driven to rotate a central angle relative to the switching hole to change a ventilation state between the switching hole and the chamber.

Abstract: A method for fabricating a semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a barrier layer in the trench, forming a nucleation layer on the barrier layer, performing an anneal process to form a silicide layer, forming a bulk layer on the silicide layer, and forming a magnetic tunneling junction (MTJ) on the bulk layer.

Abstract: A micro LED display includes a display substrate, a first soldering layer, at least one second soldering layer, first micro LEDs and at least one second micro LED. The display substrate includes a substrate having a plurality of pixel areas, a first circuit layer and a second circuit layer, and the first circuit layer and the second circuit layer are arranged in each pixel area. The first soldering layer is disposed on the first circuit layer, and the second soldering layer is disposed on the second micro LED. An arranging area of the first soldering layer is greater than an arranging area of the second soldering layer. The first micro LEDs is bonding to the first circuit layer in each pixel area through the first soldering layer. The second micro LED is bonding to the second circuit layer of one of the pixel areas through the second soldering layer.

Abstract: This invention discloses a traditional Chinese medicine, Mu Dan Pi (Moutan radicis cort), that has the potential to be used for the prevention or treatment of cachexia and muscle loss in cancer patients. The composition is a novel therapeutic agent for cachexia.

Abstract: A method of manufacturing display device is disclosed. A substrate includes a basal layer and metal contacts on the top surface. An insulation layer is disposed on the top surface and includes a first mounting surface and a bottom surface. Multiple grooves are formed on the insulation layer and each extends from the first mounting surface to the bottom surface. The grooves respectively correspond to the metal contacts and expose respective metal contacts. An electromagnetic force is provided with a direction from the basal layer toward the insulation layer. A droplet containing multiple micro components is provided on the first mounting surface. A configuration of an electrode of the micro component corresponds to a configuration of one of the grooves. The electrode is attracted to the corresponding groove by the electromagnetic force so as to electrically contact the metal contact.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.

Abstract: A micro light-emitting display device having multiple display regions is provided. The micro light-emitting display device includes a substrate, multiple micro light-emitting elements, and multiple first light-emitting auxiliary structures. The micro light-emitting elements are disposed on the substrate, and positions of the micro light-emitting elements define ranges of the display regions. The micro light-emitting elements have a same first pitch between each other in any one of the display regions. The micro light-emitting elements have a second pitch between each other at a boundary across any two adjacent display regions. The first pitch is different from the second pitch. The light-emitting auxiliary structures are respectively disposed on the micro light-emitting elements. The light-emitting auxiliary structures have a same third pitch between each other.

Abstract: A method, a system, and non-transitory computer readable medium for power and ground (P/G) routing for an integrated circuit (IC) design are provided. The method includes generating input features for a machine-learning (ML) model based on IR drop and routing congestion analysis for a P/G network for the IC design, and modifying a set of P/G vias or a set of P/G wires in the P/G network according to modifications identified by the ML model. The ML model comprises a feature extractor pre-trained using a plurality of images of P/G vias and P/G wires.

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming a first top electrode on the MTJ stack, and then forming a second top electrode on the first top electrode. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.

Abstract: A management method of cache files in storage space, adapted to a storage space storing a plurality of cache files, the management method comprises: forming a cache file status list which records a plurality of file names and a plurality of file status; determining whether a storage condition of the storage space is in a healthy condition; assigning a plurality of corresponding tags to the plurality of file status when the storage condition is not in the healthy condition, and forming a sorted cache file list; and deleting the last file name from the sorted cache file list and the cache file from the storage space corresponding to the file name, wherein the sorted cache file list records the file names which are sorted from a file name of a cache file that should be kept most to another file name of another cache file that should be deleted most.

Abstract: A micro LED display includes a display substrate, a first soldering layer, at least one second soldering layer, first micro LEDs and at least one second micro LED. The display substrate includes a substrate having a plurality of pixel areas, a first circuit layer and a second circuit layer, and the first circuit layer and the second circuit layer are arranged in each pixel area. The first soldering layer is disposed on the first circuit layer, and the second soldering layer is disposed on the second micro LED. An arranging area of the first soldering layer is greater than an arranging area of the second soldering layer. The first micro LEDs is bonding to the first circuit layer in each pixel area through the first soldering layer. The second micro LED is bonding to the second circuit layer of one of the pixel areas through the second soldering layer.

Abstract: A semiconductor structure includes a substrate; a first inter-layer dielectric (ILD) layer on the substrate; an etch stop layer on the first ILD layer; a second inter-layer dielectric (ILD) layer on the etch stop layer; and a copper damascene interconnect layer disposed in the first ILD layer. A tungsten via structure is disposed in the second ILD layer and the etch stop layer, and is electrically connected to the copper damascene interconnect layer. The tungsten via structure includes a tungsten layer and a barrier layer surrounding the tungsten layer. An intermetallic layer is disposed between the barrier layer and the copper damascene interconnect layer.

Abstract: A method and system for guided power grid augmentation determines a minimum resistance path for cells within an integrated circuit (IC) design. The minimum resistance path traces a conducting wire connecting a pin of a cell to an IC tap within the IC design. A voltage drop value for each of the cells is determined so as to identify target cells having a voltage drop value that satisfies a voltage drop criteria. Polygons have defined size characteristics are defined around the minimum resistance paths of the target cells, and conductors, such as additional conductors, are generated within the defined polygons.

Abstract: A management method of cache files in storage space, adapted to a storage space storing a plurality of cache files, the management method comprises: forming a cache file status list which records a plurality of file names and a plurality of file status; determining whether a storage condition of the storage space is in a healthy condition; assigning a plurality of corresponding tags to the plurality of file status when the storage condition is not in the healthy condition, and forming a sorted cache file list; and deleting the last file name from the sorted cache file list and the cache file from the storage space corresponding to the file name, wherein the sorted cache file list records the file names which are sorted from a file name of a cache file that should be kept most to another file name of another cache file that should be deleted most.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

Abstract: The invention provides a novel class of propiolylamide-based irreversible inhibitors of PKM2 compounds of the general formula I, pharmaceutical compositions, and methods of inducing an anti-tumor effect in a subject suffering from tumor comprising administering to the subject a pharmaceutical composition comprising an effective amount of compound of formula I.

Abstract: The invention provides a novel class of propiolylamide-based irreversible inhibitors of PKM2 compounds of the general formula I, pharmaceutical compositions, and methods of inducing an anti-tumor effect in a subject suffering from tumor comprising administering to the subject a pharmaceutical composition comprising an effective amount of compound of formula I.

Abstract: A method of manufacturing display device is disclosed. a substrate includes a basal layer and metal contacts on the top surface. An insulation layer is disposed on the top surface and includes a first mounting surface and a bottom surface. Multiple grooves are formed on the insulation layer and each extends from the first mounting surface to the bottom surface. The grooves respectively correspond to the metal contacts and expose respective metal contacts. An electromagnetic force is provided with a direction from the basal layer toward the insulation layer. A droplet containing multiple micro components is provided on the first mounting surface. A configuration of an electrode of the micro component corresponds to a configuration of one of the grooves. The electrode is attracted to the corresponding groove by the electromagnetic force so as to electrically contact the metal contact.