Abstract: A method includes following steps. A semiconductor fin is formed extending from a substrate. A gate structure is formed extending across the semiconductor fin. Recesses are etched in the semiconductor fin. Source/drain epitaxial structures are formed in the recesses in the semiconductor fin. Formation of each of the source/drain epitaxial structures comprises performing a first epitaxy growth process to form a bar-shaped epitaxial structure in one of the recesses, and performing a second epitaxy growth process to form a cladding epitaxial layer cladding on the bar-shaped epitaxial structure. The bar-shaped epitaxial structure has a lower phosphorous concentration than the cladding epitaxial layer.

Abstract: A method for tuning a threshold voltage of a transistor is disclosed. A channel layer is formed over a substrate. An interfacial layer is formed over and surrounds the channel layer. A gate dielectric layer is formed over and surrounds the interfacial layer. A dipole layer is formed over and wraps around the gate dielectric layer by performing a cyclic deposition etch process, and the dipole layer includes dipole metal elements and has a substantially uniform thickness. A thermal drive-in process is performed to drive the dipole metal elements in the dipole layer into the gate dielectric layer to form an interfacial dipole surface, and then the dipole layer is removed.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A method for performing interactive operation upon a stereoscopic image and a stereoscopic image display system are provided. The stereoscopic image display system includes a stereoscopic display and a gesture sensor. In the method, the stereoscopic display displays the stereoscopic image, and the gesture sensor senses a gesture. A current gesture state is obtained. A previous state of the stereoscopic image and a previous gesture state are obtained. Stereo coordinate variations corresponding to the gesture can be calculated according to the current gesture state and the previous gesture state. New stereoscopic image data can be obtained according to the previous state of the stereoscopic image and the stereo coordinate variations corresponding to the gesture. The stereoscopic display is used to display a new stereoscopic image that is rendered from the new stereoscopic image data.

Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.

Abstract: A backlight module includes a light guide plate, a light source, a first prism sheet, and a second prism sheet. The light source is disposed on a light incident surface of the light guide plate. The first prism sheet is disposed on a side of a light exiting surface of the light guide plate and has multiple first prism structures facing the light guide plate. The second prism sheet has multiple second prism structures facing the light guide plate. An included angle between an extending direction of the first prism structures and an extending direction of the second prism structures is greater than or equal to 85 degrees and less than or equal to 95 degrees. An included angle between the extending direction of the second prism structures and the light incident surface is greater than or equal to 85 degrees and less than or equal to 95 degrees.

Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: An electronic device and a method for accelerating canonical polyadic (CP) decomposition are provided. The method includes: performing at least one of a Walsh-Hadamard transform (WHT) operation and a discrete cosine transform (DCT) operation on a first factor matrix, a second factor matrix, and a tensor respectively to update the first factor matrix, the second factor matrix and the tensor; sampling the updated first factor matrix and the updated second factor matrix to generate a first sampled matrix, and sampling an unfolded matrix of the updated tensor to generate a second sampled matrix; solving a least square problem of the first sampled matrix and the second sampled matrix to generate or update a third factor matrix of the tensor so as to update multiple components of the tensor; and outputting multiple components after an updating of multiple components is finished.

Abstract: An electronic device includes a casing, a circuit board and at least one antenna module. The casing has an accommodating space and an inner side wall surrounding the accommodating space. The circuit board is disposed in the accommodating space. Each of the antenna modules includes a first radiator and a second radiator. The first radiator is disposed on the circuit board and adjacent to the inner side wall, and includes a first section, a second section and a third section extending from the first section in opposite directions respectively. The first section includes a feeding end, and the third section includes a grounding end. The second radiator is disposed on the inner side wall. A coupling gap is formed between the first radiator and the second radiator.

Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

Abstract: An electronic device including a metal bottom plate, a metal frame and at least one radiator is provided. The metal bottom plate includes at least one ground terminal. The metal frame includes at least one slot, at least one disconnecting part, at least one first connecting part and at least one second connecting part. The disconnecting part includes a first part and a second part. Each radiator includes a first terminal and a second terminal. The second terminal is connected to a junction between the first part and the second part. The first terminal, the second terminal, the first part, the first connecting part and the ground terminal form a first antenna path radiating at a first frequency band. The first terminal, the second terminal, the second part, the second connecting part and the ground terminal form a second antenna path radiating at a second frequency band.

Abstract: Disclosed is a light-emitting diode display module, including a first light-emitting diode, a second light-emitting diode, a third light-emitting diode, a scan block, a voltage conversion block, a first sink block, and a second sink block. An operating voltage of the first light-emitting diode is lower than that of the second and third light-emitting diodes. The voltage conversion block provides an auxiliary power supply voltage based on a high power supply voltage and a low power supply voltage. The first light-emitting diode is coupled between the scan block and the first sink block receiving the high power supply voltage and the auxiliary power supply voltage. The second light-emitting diode and the third light-emitting diode are coupled between the scan block and the second sink block receiving the high power supply voltage and the low power supply voltage.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.

Abstract: A speed-reducer-and-motor all-on-one machine is disclosed and includes a connection shaft, a motor and a speed reducer. The connection shaft includes a first section, a second section and an accommodation space. The first section and the second section are arranged in an axial direction. The accommodation space is in communication between a front end and a rear end of the connection shaft. An elliptical cam is formed on an outer surface of the second section of the connection shaft. An outer diameter of the first section is greater than a major axis length of the elliptical cam. The motor is received within the accommodation space and connected to an inner surface of the first section. The speed reducer is connected to the outer surface of the second section.

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.

Abstract: A portable genome sequencing and genotyping device includes a sample processing module, a sequencing module, an analyzing module, and a communication module. The sample processing module is configured to process a sample so as to generate at least one DNA segment of the sample. The sequencing module is connected to the sample processing module, and is configured to generate a number of base sequences corresponding to the at least one DNA segment. The analyzing module is coupled to the sequencing module, and is configured to generate a genotyping analysis result based on the base sequences. The communication module is configured to receive the genotyping analysis result and transmit the genotyping analysis result to a user terminal.