Patents by Inventor Hsiang-An Yang

Hsiang-An Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11855066
    Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
  • Publication number: 20230412045
    Abstract: A speed-reducer-and-motor all-on-one machine is disclosed and includes a connection shaft, a motor and a speed reducer. The connection shaft includes a first section, a second section and an accommodation space. The first section and the second section are arranged in an axial direction. The accommodation space is in communication between a front end and a rear end of the connection shaft. An elliptical cam is formed on an outer surface of the second section of the connection shaft. An outer diameter of the first section is greater than a major axis length of the elliptical cam. The motor is received within the accommodation space and connected to an inner surface of the first section. The speed reducer is connected to the outer surface of the second section.
    Type: Application
    Filed: April 19, 2023
    Publication date: December 21, 2023
    Inventors: Chi-Wen Chung, Hung-Wei Lin, Fu-Kuang Yang, Shu-Hsiang Yang, Tzu-Min Yi
  • Publication number: 20230411215
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.
    Type: Application
    Filed: July 28, 2023
    Publication date: December 21, 2023
    Inventors: Shao-Ming YU, Tung Ying LEE, Wei-Sheng YUN, Fu-Hsiang YANG
  • Patent number: 11840729
    Abstract: A portable genome sequencing and genotyping device includes a sample processing module, a sequencing module, an analyzing module, and a communication module. The sample processing module is configured to process a sample so as to generate at least one DNA segment of the sample. The sequencing module is connected to the sample processing module, and is configured to generate a number of base sequences corresponding to the at least one DNA segment. The analyzing module is coupled to the sequencing module, and is configured to generate a genotyping analysis result based on the base sequences. The communication module is configured to receive the genotyping analysis result and transmit the genotyping analysis result to a user terminal.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: December 12, 2023
    Assignees: NATIONAL CHIAO TUNG UNIVERSITY, NATIONAL TAIWAN UNIVERSITY
    Inventors: Jui-Hung Hung, Chia-Hsiang Yang
  • Patent number: 11829731
    Abstract: A modular multiplication circuit includes a main operation circuit, a look-up table, and an addition unit. The main operation circuit updates a sum value and a carry value according to 2iA corresponding to a first operation value A and m bits of a second operation value B currently under operation, m is a positive integer, i is from 0 to m?1. The look-up table records values related to a modulus, and selects one of the values as a look-up table output value according to the sum value. The addition unit updates the sum value and the carry value according to the look-up table output value and outputs the updated sum value and the updated carry value to the main operation circuit. The modular multiplication circuit updates the sum value and the carry value in a recursive manner by using m different bits of the second operation value B.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: November 28, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Hsiang Yang, Liang-Hsin Lin, Yu-Ling Kang, Li-Chi Su
  • Patent number: 11814465
    Abstract: An organic-inorganic hybrid material is disclosure. The organic-inorganic hybrid material contains 5˜50 wt % of inorganic compounds and has a characteristic peak at 1050±50 cm?1 in FTIR spectrum. Furthermore, the invention also provides a fabricating process of the organic-inorganic hybrid material as well as its starting material “isocyanates”. In particular, the isocyanates are prepared from carbonate containing compounds and amines.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: November 14, 2023
    Assignee: CHANDA CHEMICAL CORP.
    Inventors: Sheng-hong A. Dai, Chien-Hsin Wu, Ying-Chi Huang, Yu-Hsiang Huang, Shih-Chieh Yeh, Ru-Jong Jeng, Jau-Hsiang Yang
  • Publication number: 20230335196
    Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
    Type: Application
    Filed: June 20, 2023
    Publication date: October 19, 2023
    Inventors: Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang, Chia-Sheng Lin, ShihKuang Yang, Yu-Chun Chang, Hung-Ling Shih, Po-Wei Liu, Shih-Hsien Chen
  • Patent number: 11791444
    Abstract: A display apparatus including a circuit substrate, a plurality of light-emitting elements, an optical film, and an adhesive layer is provided. These light-emitting elements are electrically bonded to the circuit substrate. The optical film overlaps the light-emitting elements. The light-emitting elements are disposed between the optical film and the circuit substrate. The adhesive layer is disposed between the optical film and the circuit substrate, and connects the light-emitting elements and the optical film. A cavity is provided between the light-emitting elements, the circuit substrate, and the adhesive layer.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: October 17, 2023
    Assignee: Au Optronics Corporation
    Inventors: Chih-Wei Chien, Chih-Hsiang Yang, Shau-Yu Tsai, Cheng-Chuan Chen, Chih-Ling Hsueh
  • Patent number: 11784159
    Abstract: Provided are a mass transfer device and a mass transfer method. The mass transfer device is provided with multiple channels, a first opening of each channel is arranged on a first surface of the mass transfer device, a second opening of each channel is arranged on a second surface of the mass transfer device, and the distances between the channels are gradually increased along a direction from the first surface to the second surface. In the provided mass transfer method, through a laser irradiation mode, the Micro-LEDs are separated from the first substrate and enter the channels of the mass transfer device through the first openings, and falling into Micro-LED to-be-installed positions on a second substrate through the second openings of the channels, thereby transferring the Micro-LEDs from the first substrate to the second substrate.
    Type: Grant
    Filed: May 8, 2021
    Date of Patent: October 10, 2023
    Assignee: CHONGQING KONKA PHOTOELECTRIC TECHNOLOGY RESEARCH INSTITUTE CO., LTD.
    Inventors: Jan-hsiang Yang, Kai-yi Wu, Chia-hui Shen, Jen-chieh Chiang
  • Publication number: 20230312377
    Abstract: A non-membrane deionization and ion-concentrating apparatus is connected to a power supply and includes a microfluidic channel, two current collectors and an electroactive material. The microfluidic channel is disposed between the two current collectors, and the power supply applies a voltage to the two current collectors. The electroactive material is coated and connected to at least one of the two current collectors, wherein the electroactive material has a reversible redox ability.
    Type: Application
    Filed: October 7, 2022
    Publication date: October 5, 2023
    Inventors: Chi-Chang HU, Yi-Heng TU, Yu-Hsiang YANG, Jen-Huang HUANG
  • Patent number: 11776852
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Ming Yu, Tung Ying Lee, Wei-Sheng Yun, Fu-Hsiang Yang
  • Patent number: 11778165
    Abstract: A floating three-dimensional image display system is provided. The floating three-dimensional image display system includes a controller and a first floating image display device. The controller converts a plurality of image information of an electronic device into a plurality of first floating image information according to the plurality of image information and a plurality of depth information of the electronic device, and displays the plurality of first floating image information in a space above a first side of the first floating image display device through the first floating image display device.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: October 3, 2023
    Assignee: Lixel Inc.
    Inventors: Chun-Hsiang Yang, Chih-Hung Ting, Kai-Chieh Chang
  • Publication number: 20230301117
    Abstract: A memory device includes a substrate, a first conductive stripe disposed on the substrate and extending along a first direction, a second conductive stripe disposed on the first conductive stripe, a first pillar element and a spacer. The second conductive stripe extends along a second direction intersected with the first direction. A thickness of the second conductive stripe is greater than a thickness of the first conductive stripe, and the second conductive stripe is an integral structure. The first pillar element is disposed at an intersection between the first conductive stripe and the second conductive stripe, and extends from a top surface of the first conductive stripe to a bottom surface of the second conductive stripe along a third direction intersected with the first direction and the second direction. The first pillar element includes a switching layer and a memory layer corresponding to a first level.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Inventors: Erh-Kun LAI, Hsiang-Lan LUNG, Chih-Hsiang YANG
  • Publication number: 20230282144
    Abstract: An arcuate display device includes a plurality of display units each having has a plurality of pixels, a virtual axis, and a plurality of driving devices. Each pixel includes first, second, and third light-emitting elements respectively disposed at first, second, and third positions. The driving devices corresponding to the display units having the same minimum distance from the virtual axis have the same circuit layout design. The first, second, and third positions are sequentially arranged in a direction away from the virtual axis. Optical properties of the first light-emitting elements and the third light-emitting elements in at least a part of the pixels disposed at a first side of the virtual axis are respectively substantially the same as optical properties of the third light-emitting elements and the first light-emitting elements in at least a part of the pixels disposed at a second side of the virtual axis.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 7, 2023
    Applicant: AUO Corporation
    Inventors: Kai-Yi Lu, Hung-Chi Wang, Chen-Yu Lin, Ya-Fang Chen, Chih-Hsiang Yang
  • Publication number: 20230282160
    Abstract: Disclosed is a light-emitting diode display module, including a first light-emitting diode, a second light-emitting diode, a third light-emitting diode, a scan block, a voltage conversion block, a first sink block, and a second sink block. An operating voltage of the first light-emitting diode is lower than that of the second and third light-emitting diodes. The voltage conversion block provides an auxiliary power supply voltage based on a high power supply voltage and a low power supply voltage. The first light-emitting diode is coupled between the scan block and the first sink block receiving the high power supply voltage and the auxiliary power supply voltage. The second light-emitting diode and the third light-emitting diode are coupled between the scan block and the second sink block receiving the high power supply voltage and the low power supply voltage.
    Type: Application
    Filed: February 21, 2023
    Publication date: September 7, 2023
    Applicant: AUO Corporation
    Inventors: Chung-Hsien Hsu, Chi-Yu Geng, Shu-Hao Chang, Hung-Chi Wang, Ming-Hung Tu, Ya-Fang Chen, Chih-Hsiang Yang
  • Publication number: 20230207536
    Abstract: The present disclosure provides a display device, including first to fourth LEDs, a line structure, and first to fourth lines. The second LED is arranged in a first direction corresponding to the first LED. The fourth LED is arranged in a second direction corresponding to the third LED. The line structure includes first to third line segments. The first line is coupled to the first LED. The second line is coupled to the second LED. The third line is coupled to the third LED. The fourth line is coupled to the fourth LED. A portion of the first line and a portion of the second line are in parallel with the first line segment, a portion of the third line is in parallel with the second line segment, and a portion of the fourth line is in parallel with the third line segment.
    Type: Application
    Filed: July 12, 2022
    Publication date: June 29, 2023
    Inventors: Jeng-Lin CAI, Chung-Hsien HSU, Ming-Hung TU, Ya-Fang CHEN, Chih-Hsiang YANG
  • Patent number: 11687166
    Abstract: An image processing system and an image processing device are provided. The image processing system includes an electronic device and the image processing device. The image processing device is connected to the electronic device. The image processing device displays a floating three-dimensional input device image information. The image processing device interacts with an object through the three-dimensional input device image information to generate a plurality of control signals, and transmits the plurality of control signals to the electronic device.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: June 27, 2023
    Assignee: LIXEL INC.
    Inventors: Chun-Hsiang Yang, Chih-Hung Ting, Kai-Chieh Chang, Ta-Kai Lin, Yu-Hsien Li
  • Patent number: 11683469
    Abstract: A stereoscopic image display device is provided and includes a flat panel display unit, a lens array unit, and a spacer unit. The flat panel display unit has a display surface. The lens array unit includes at least one condenser lens, which is disposed on a side of the display surface. The spacer unit is disposed between the display surface and the condenser lens, such that the lens array unit and the flat panel display unit are spaced apart from each other. In a light field system of the stereoscopic image display device, an object distance between the display surface of the flat panel display unit and the condenser lens of the lens array unit is configured to enable an absolute value of a central depth plane (CDP) of the stereoscopic image display device in the light field system to be between 1 mm and 200 mm.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: June 20, 2023
    Assignee: Lixel Inc.
    Inventors: Chun-Hsiang Yang, Chih-Hung Ting, Kai-Chieh Chang, Hsin-You Hou, Kuan-Yu Chen
  • Publication number: 20230185237
    Abstract: A holographic energy system is operable to generate an output wavefront according to a complex amplitude function. The holographic energy system includes a continuous three-dimensional energy medium, an array of energy devices configured to output energy to interact with the continuous three-dimensional energy medium to define a hologram therein, and an electromagnetic (EM) energy source positioned to output coherent EM energy that is incident on the hologram in the continuous three-dimensional energy medium to generate an output wavefront.
    Type: Application
    Filed: November 18, 2022
    Publication date: June 15, 2023
    Inventors: Chih-Hsiang Yang, Jonathan Sean Karafin, Brendan Elwood Bevensee
  • Publication number: 20230168742
    Abstract: A method for performing interactive operation upon a stereoscopic image and a stereoscopic image display system are provided. The stereoscopic image display system includes a stereoscopic display and a gesture sensor. In the method, the stereoscopic display displays the stereoscopic image, and the gesture sensor senses a gesture. A current gesture state is obtained. A previous state of the stereoscopic image and a previous gesture state are obtained. Stereo coordinate variations corresponding to the gesture can be calculated according to the current gesture state and the previous gesture state. New stereoscopic image data can be obtained according to the previous state of the stereoscopic image and the stereo coordinate variations corresponding to the gesture. The stereoscopic display is used to display a new stereoscopic image that is rendered from the new stereoscopic image data.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 1, 2023
    Inventors: ARVIN LIN, YUNG-CHENG CHENG, CHUN-HSIANG YANG