Patents by Inventor Hsiang Chen

Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250252031
    Abstract: Disclosed are a method for visual aid prompts and an electronic apparatus thereof. After a sensor adjacent to a connection interface configured on a display is driven for operation, when the sensor detects an object entering a specified range, a processor provides a driving signal to the display. The display presents at least one graphical interface on the display screen according to the driving signal, and the graphical interface includes a schematic diagram corresponding to the connection interface. The processor determines whether the connection interface is being used, and further dynamically adjusts a content presented by the graphical interface.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 7, 2025
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Yung-Hsiang Chen, Li-Wei Hung, Hung-Chieh Wu
  • Patent number: 12374530
    Abstract: A Faraday shield, a semiconductor processing apparatus, and an etching apparatus are provided. The Faraday shield includes a plurality of conductive slices and a spacer interposed between adjacent two of the conductive slices to electrically isolate the adjacent two of conductive slices from one another. The conductive slices are separately arranged aside one another and oriented along a circumference of the Faraday shield. A coil is wound around the circumference of the Faraday shield.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsiang Chen, Ching-Horng Chen, Yen-Ji Chen, Cheng-Yi Huang, Chih-Shen Yang
  • Publication number: 20250238084
    Abstract: A method, system, apparatus, and/or device for moving or scrolling a virtual object in a virtual or augmented reality environment. The method, system, apparatus, and/or device may include: detecting, by a first sensor, a first gesture associated with selecting a first virtual object in an augmented reality environment displayed by a head-mounted display; displaying, by the head-mounted display, a first indicator indicating a selection of the first virtual object by a user; detecting, using the first sensor or a second sensor, a first movement of the head-mounted display associated with a first movement command; and in response to detecting the first movement of the head-mounted display, executing the first movement command, where the first movement command is a scrolling function to scroll text or a graphical object of the first virtual object or a movement function to move the text or the graphical object of the first virtual object.
    Type: Application
    Filed: September 4, 2024
    Publication date: July 24, 2025
    Inventors: Yu-Hsiang Chen, Soulaiman Itani
  • Publication number: 20250240011
    Abstract: An electronic circuit is provided. The electronic circuit includes an electronic element, a driving transistor, a first emitting transistor, a first reset transistor and a capacitor. The driving transistor is electrically connected to the electronic element. A power voltage is passed through the driving transistor to drive the electronic element. A first terminal of the first emitting transistor is electrically connected to the power voltage. A terminal of the first reset transistor receives the reset signal. A first terminal of the capacitor is electrically connected to a control terminal of the driving transistor. A second terminal of the capacitor is electrically connected to the first reset transistor and the first emitting transistor. When the electronic element is driven, a first terminal of the driving transistor and the first terminal of the first emitting transistor receive the power voltage.
    Type: Application
    Filed: December 19, 2024
    Publication date: July 24, 2025
    Applicant: Innolux Corporation
    Inventors: Yong-Zhi Liu, Lien-Hsiang Chen, Ming-Chun Tseng
  • Patent number: 12369422
    Abstract: The present disclosure relates to a CMOS image sensor. The image sensor comprises a pixel region comprising a photodiode disposed within a substrate. A deep trench isolation (DTI) ring encloses the photodiode from top view and extends from a back-side to a first position within the substrate from cross-sectional view. A pair of shallow trench isolation (STI) structures is respectively disposed at an inner periphery and an outer periphery sandwiching the DTI ring from top view and extends from a front-side to a second position within the substrate from cross-sectional view. A pixel device is disposed at the front-side of the substrate directly overlying the DTI ring. The pixel device comprises a gate electrode disposed over the substrate and a pair of source/drain (S/D) regions disposed within the substrate and reaching on a top surface of the DTI ring.
    Type: Grant
    Filed: April 17, 2024
    Date of Patent: July 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Seiji Takahashi, Jhy-Jyi Sze, Tzu-Hsiang Chen
  • Patent number: 12369336
    Abstract: A semiconductor processing system is provided to form a capacitor dielectric layer in a metal-insulator-metal capacitor. The semiconductor processing system includes a precursor tank configured to generate a precursor gas from a metal organic solid precursor, a processing chamber configured to perform a plasma enhanced chemical vapor deposition, and at least one buffer tank between the precursor tank and the processing chamber. The at least one buffer tank is coupled to the precursor tank via a first pipe and coupled to the processing chamber via a second pipe.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: July 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Liang Chen, Yu-Lung Yeh, Chihchous Chuang, Yen-Hsiu Chen, Tsai-Ji Liou, Yung-Hsiang Chen, Ching-Hung Huang
  • Patent number: 12361993
    Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.
    Type: Grant
    Filed: April 15, 2024
    Date of Patent: July 15, 2025
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hsiang-Chi Cheng, Shyh-Bin Kuo, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsien Yang, Yu-Chih Wang, Kuo-Hsiang Chen
  • Patent number: 12361734
    Abstract: The present application discloses a method for detecting image by using semantic segmentation. To input an image with data augmentation, and then encode and decode using a neural network. At least one semantically divided, and finally the at least one semantically divided is compared with the sample to classify as a target or a non-target. In this way, the CNN is used to detect whether the image is the SCC image or not, and locate the section, thereby assisting the doctor in interpreting the esophagus image.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: July 15, 2025
    Assignee: National Chung Cheng University
    Inventors: Hsiang-Chen Wang, Kuan-Lin Chen, Yu-Ming Tsao, Jen-Feng Hsu
  • Patent number: 12363928
    Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.
    Type: Grant
    Filed: March 27, 2024
    Date of Patent: July 15, 2025
    Inventors: Ting-Ying Wu, Yung-Hsiang Chen, Yu-Lung Yeh, Yen-Hsiu Chen, Wei-Liang Chen, Ying-Tsang Ho
  • Patent number: 12364103
    Abstract: A display device includes: a substrate; a first transistor and a second transistor disposed on the substrate; a first electrode and a second electrode, wherein the first electrode is electrically connected to the first transistor through a first via hole, and the second electrode is electrically connected to the second transistor through a second via hole; a first signal line disposed on the substrate and overlapped with the first electrode and the second electrode; and a second signal line disposed on the substrate and adjacent to the first signal line, wherein the first signal line and the second signal line extend along a first direction, wherein a distance between the first via hole and the second via hole along the first direction is greater than a distance between the first signal line and the second signal line along a second direction different the first direction.
    Type: Grant
    Filed: May 9, 2024
    Date of Patent: July 15, 2025
    Assignee: Red Oak Innovations Limited
    Inventors: Lien-Hsiang Chen, Kung-Chen Kuo, Sheng-Kai Hsu, Hsia-Ching Chu, Mei-Chun Shih
  • Patent number: 12364105
    Abstract: A display device includes: a substrate; a first transistor and a second transistor disposed on the substrate; a first electrode and a second electrode, wherein the first electrode is electrically connected to the first transistor through a first via hole, and the second electrode is electrically connected to the second transistor through a second via hole; a first signal line disposed on the substrate and overlapped with the first electrode and the second electrode; and a second signal line disposed on the substrate and adjacent to the first signal line, wherein the first signal line and the second signal line extend along a first direction, wherein a distance between the first via hole and the second via hole along the first direction is greater than a distance between the first signal line and the second signal line along a second direction different the first direction.
    Type: Grant
    Filed: January 17, 2025
    Date of Patent: July 15, 2025
    Assignee: Red Oak Innovations Limited
    Inventors: Lien-Hsiang Chen, Kung-Chen Kuo, Sheng-Kai Hsu, Hsia-Ching Chu, Mei-Chun Shih
  • Publication number: 20250221667
    Abstract: A monitoring auxiliary device includes an outer surface layer, an inner surface layer, a middle layer, at least two electrode points, at least two conducting wires and at least two conducting sheets. The middle layer is located between the outer surface layer and the inner surface layer. The electrode points include a first electrode point and a second electrode point. The conducting wires include a first conducting wire and a second conducting wire. The conducting sheets include a first conducting sheet and a second conducting sheet. The electrode points are disposed on the outer surface layer of the monitoring auxiliary device, the conducting sheets are disposed on the inner surface layer of the monitoring auxiliary device.
    Type: Application
    Filed: December 18, 2024
    Publication date: July 10, 2025
    Inventors: Cheng-Kuo LAI, Yuan-Yen YAO, Chen-Hsiang CHEN, Yu Jie HONG, Chun-Hung TENG
  • Patent number: 12347770
    Abstract: An interconnect structure according to the present disclosure includes a first dielectric layer, a first conductive feature and a second conductive feature in the first dielectric layer, a first dielectric feature disposed directly on the first conductive feature; a first etch stop layer (ESL) disposed over the first dielectric layer and the second conductive feature, a first conductive layer disposed on and in contact with the first dielectric feature, a second ESL disposed over the first conductive layer, a second dielectric layer disposed directly on the first ESL and the second ESL, a first via extending through the second dielectric layer and the second ESL to contact with the first conductive feature, and a second via extending through the second dielectric layer and the first ESL to contact with the second conductive feature.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hsiang Chen, Wen-Sheh Huang, Po-Hsiang Huang, Hsiu-Wen Hsueh
  • Patent number: 12345986
    Abstract: An electronic device with switchable modes includes a light scattering switching element, a light absorbing switching and an image generating element. The light absorbing switching element is disposed adjacent to the light scattering switching element. The image generating element is provided for generating an image. In a projection mode, the image generated by the image generating element sequentially passes through the light scattering switching element and the light absorbing switching element to be displayed.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: July 1, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: De-Cheng Chung, Hsu-Kuan Hsu, En-Hsiang Chen, Chih-Chin Kuo, Tzu-Chieh Lai
  • Patent number: 12345970
    Abstract: An electrically controlled panel including a first electrically controlled device including first and second alignment layers and a first liquid-crystal layer disposed therebetween, a first polarizing layer, and a first compensation film disposed at a side of the first polarizing layer provided with the first electrically controlled device is provided. The first and second alignment layers have first and second alignment directions respectively. An included angle between the first and second alignment directions is between 75 degrees and 105 degrees. A phase retardation of the first liquid-crystal layer is between 400 nm and 600 nm or between 800 nm and 1200 nm. The first polarizing layer is disposed at a side of the first alignment layer away from the first liquid-crystal layer, and has a first absorption axis parallel to or perpendicular to the first alignment direction. A display apparatus adopting the electrically controlled panel is also provided.
    Type: Grant
    Filed: September 9, 2024
    Date of Patent: July 1, 2025
    Assignee: Coretronic Corporation
    Inventors: Ping-Yen Chen, Hsin Huang, Chung-Yang Fang, Ying-Hsiang Chen
  • Publication number: 20250210610
    Abstract: A package structure and a method for forming a package structure are provided. The package structure includes a chip-containing structure bonded to a redistribution structure through multiple first solder bumps. The package structure also includes a memory-containing structure bonded to an interposer chip. The interposer chip is bonded to the redistribution structure through multiple second solder bumps. The package structure further includes a substrate, and the redistribution structure is over the substrate.
    Type: Application
    Filed: April 25, 2024
    Publication date: June 26, 2025
    Inventors: Po-Yu Chen, Yu Hsiang Chen
  • Patent number: 12341553
    Abstract: A signal transmitter may include a waveform synthesis circuit and a signal transmission circuit. The waveform synthesis circuit may store values of a reference waveform for a selected channel of the signal transmitter, and use the stored values to generate values of reference waveforms for one or more other channels of the signal transmitter. The waveform synthesis circuit may further include a sampling boost circuit to generate one or more additional values for the reference waveforms. The waveform transmission circuit may generate signals for the channels of the signal transmitter based at least in part on the values of the reference waveforms, and transmit the signals via one or more antennas.
    Type: Grant
    Filed: November 2, 2023
    Date of Patent: June 24, 2025
    Assignee: Apple Inc.
    Inventors: Long Kong, Chia-Hsiang Chen, Utku Seckin
  • Publication number: 20250201789
    Abstract: An electronic device comprises: a first panel comprising: a first display layer having a first side and a second side opposite thereto, wherein the first display layer receives an incident light and reflects a first reflected light, a light in the incident light other than the first reflected light is a first transmitting light, the first side is a light emitting side of the first reflected light, and the second side is a transmitting side of the first transmitting light; a first photoelectric conversion unit disposed adjacent to the second side, wherein the first photoelectric conversion unit absorbs the first transmitting light and converts it into electrical energy; and a second panel disposed opposite to the first panel, wherein the second panel comprises a second display layer, and the first photoelectric conversion unit is disposed between the first display layer and the second display layer.
    Type: Application
    Filed: November 20, 2024
    Publication date: June 19, 2025
    Inventors: Hsu-Kuan HSU, Tzu-Chieh LAI, Chih-Chin KUO, En-Hsiang CHEN, WenQi LIN, Mao-Shiang LIN
  • Publication number: 20250190677
    Abstract: A phase shifter includes a first transistor, and a second transistor coupled to the first transistor. The first transistor includes an active region extending in a first direction, and a first set of gates extending in a second direction. The first set of gates overlaps the active region and is configured to receive a first voltage. The first transistor is configured to adjust a resistance or a first capacitance of the phase shifter responsive to the first voltage. The second transistor includes the active region, and a second set of gates extending in the second direction. The second set of gates overlaps the active region, is positioned along opposite edges of the active region, and is configured to receive a second voltage. The second transistor is configured to adjust a second capacitance of the phase shifter responsive to the second voltage.
    Type: Application
    Filed: February 18, 2025
    Publication date: June 12, 2025
    Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Publication number: 20250192900
    Abstract: A calibration method to find the impedance of a radio frequency front-end (RFFE) is provided. The RFFE includes a feedback end and a tuner. The tuner is set to a first predetermined setting to have a first impedance. An output end of the tuner is set to different calibration settings. The first reflection coefficient sets at the feedback end is obtained. The second impedance from the feedback end of the RFFE to an input end of the tuner is calculated based on the first reflection coefficient. The tuner is set to a second predetermined setting. The second reflection coefficient sets at the feedback end is obtained. The third impedance of the tuner in the second predetermined setting is calculated based on the second impedance from the feedback end of the RFFE to the input end of the tuner and the second reflection coefficient sets.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 12, 2025
    Inventors: Chun-Hsiang CHEN, Chin-Wei HSU, Po-Chung HSIAO, Sin-Sheng WONG, Yen-Liang CHEN