Patents by Inventor Hsiang Chen

Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210375762
    Abstract: A method of manufacturing a semiconductor device based on a dual-architecture-compatible design includes: forming transistor components of in a transistor (TR) layer; and performing one of fabricating additional components according to (A) a buried power rail (BPR) type of architecture or (B) a non-buried power rail (non-BPR) type of architecture. The step (A) includes, in corresponding sub-TR layers, forming various non-dummy sub-TR structures, and, in corresponding supra-TR layers, forming various dummy supra-TR structures which are corresponding first artifacts. The step (B) includes, in corresponding supra-TR layers, forming various non-dummy supra-TR structures and forming various dummy supra-TR structures which are corresponding second artifacts, the first and second artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR type of architecture.
    Type: Application
    Filed: March 9, 2021
    Publication date: December 2, 2021
    Inventors: Chung-Hui CHEN, Cheng-Hsiang HSIEH, Wan-Te CHEN, Tzu Ching CHANG, Wei Chih CHEN, Ruey-Bin SHEEN, Chin-Ming FU
  • Publication number: 20210375853
    Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first conductive pattern over the active region, and a second conductive pattern under the second side of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically coupled to the first portion and the second portion of the active region. The second conductive pattern is electrically coupled to the first portion and the second portion of the active region.
    Type: Application
    Filed: March 2, 2021
    Publication date: December 2, 2021
    Inventors: Chung-Hui CHEN, Tzu-Ching CHANG, Cheng-Hsiang HSIEH
  • Publication number: 20210374519
    Abstract: A method for generating a classification model using a training data set. An iterative procedure for training an ANN model, in which an iteration includes selecting a small sample of training data from a source of training data, training the model using the sample, using the model in inference mode over a larger sample of the training data, and reviewing the results of the inferencing. The results can be evaluated to determine whether the model is satisfactory, and if it does not meet specified criteria, then cycles of sampling, training, inferencing and reviewing results (STIR cycles) are repeated in an iterative process until the criteria are met. A classification engine trained as described herein is provided.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Hung CHEN, Tzu-Hsiang SU
  • Publication number: 20210373533
    Abstract: A method for predicting and compensating frictions of a feed system includes following steps: constantly obtaining current signals and angle-position signals of a motor by a motor driver of a feed system after being activated; calculating frictions of the motor upon each rotating position according to the obtained current signals and angle-position signals and generating multiple records of friction data; creating a friction model according to the multiple records of friction data and the angle-position signals each respectively corresponding to each record of friction data with respect to each rotating position; importing current angle-position signal of the motor to the friction model for predicting a predicted friction; calculating a compensation current based on the predicted friction; and, controlling the motor driver to additionally provide the compensation current to the motor for conquering an upcoming friction of the feed system approximate to the predicted friction.
    Type: Application
    Filed: September 24, 2020
    Publication date: December 2, 2021
    Inventors: Chia-Yen LEE, Yu-Hsiang CHENG, Chia-Hui CHEN, Ping-Chun TSAI
  • Publication number: 20210371169
    Abstract: A bowl and lid set includes a lid member that has a top lid wall and a first surrounding wall extending downwardly from the top lid wall, and a bowl member that includes a bottom wall and a side wall extending upwardly from a periphery of the bottom wall. The side wall has an upper engaging portion that is made of an elastic material and that is deformable from a non-deformed state, where the bowl member is disengaged from the lid member and where a minimum inner diameter of the upper engaging portion is smaller than a maximum outer diameter of the first surrounding wall of the lid member, to a deformed state, where the upper engaging portion is resiliently stretched for tightly encircling the first surrounding wall.
    Type: Application
    Filed: December 22, 2020
    Publication date: December 2, 2021
    Inventor: Yu-Hsiang CHEN
  • Publication number: 20210373739
    Abstract: A method for touch sensing enhancement implemented in a single chip, a single chip capable of achieving touch sensing enhancement, and a computing apparatus are introduced. The single chip is used to be coupled to a display panel with a touch sensor and a fingerprint sensor. The computing apparatus may include the display panel, the single chip, and a processing unit, wherein the single chip is coupled between the display panel and processing unit. The method includes obtaining touch sensing data by a touch sensing module disposed within the single chip and coupled to the touch sensor; obtaining fingerprint sensing data by a fingerprint sensing module disposed within the single chip and coupled to the fingerprint sensor; and generating output touch data based on the touch sensing data and the fingerprint sensing data. With the contribution of the fingerprint sensing data, touch sensing enhancement can be achieved.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Jyun-Sian Li, Yun-Hsiang Yeh, Yen-Heng Chen
  • Publication number: 20210374949
    Abstract: The present application related to a method for detecting an object image using a convolutional neural network. Firstly, obtaining feature images by Convolution kernel, and then positioning an image of an object under detected by a default box and a boundary box from the feature image. By Comparing with the sample image, the detected object image is classifying to an esophageal cancer image or a non-esophageal cancer image. Thus, detecting an input image from the image capturing device by the convolutional neural network to judge if the input image is the esophageal cancer image for helping the doctor to interpret the detected object image.
    Type: Application
    Filed: October 27, 2020
    Publication date: December 2, 2021
    Inventors: HSIANG-CHEN WANG, HAO-YI SYU, TSUNG-YU YANG, YU-SHENG CHI
  • Publication number: 20210373069
    Abstract: A signal testing device and a signal testing method are provided. The method includes: obtaining, through a probe, a first frequency response corresponding to a test fixture and a device under test (DUT); obtaining, through the probe, a second frequency response corresponding to the test fixture; and generating a frequency response corresponding to the DUT according to the first frequency response, the second frequency response, a de-embedding algorithm, and an empirical mode decomposition algorithm.
    Type: Application
    Filed: July 20, 2020
    Publication date: December 2, 2021
    Applicant: Wiwynn Corporation
    Inventors: Kuan-Wei Chen, Tzu-Yu Wei, Yi-Shian Chen, Yi-Tang Chen, Chi-Hsiang Hung, Ting-Kai Wang
  • Publication number: 20210373420
    Abstract: A projecting apparatus is provided, and includes a frame, a light source module, at least one collimator lens, at least one adhesive, and a microelectromechanical systems (MEMS) module. The frame includes a first frame portion and a second frame portion. The first frame portion has a carrier and a carrying bridge having an end connected to the carrier. The frame has a processing slot that uses the carrying bridge as a bottom thereof, and the carrying bridge has at least one thru-hole that is in spatial communication with the processing slot. The second frame portion is connected to the carrier and another end of the carrying bridge of the first frame portion. The at least one adhesive corresponds in position to the at least one thru-hole, and connects the at least one collimator lens onto the carrying bridge. The MEMS module is disposed on the second frame portion.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 2, 2021
    Inventors: MAKOTO MASUDA, WEN-CHIEH WU, HSIANG-CHEN HO, CHIH-HAN YEN, CHIH-YU YANG
  • Patent number: 11189596
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Patent number: 11189238
    Abstract: A display device receiving image data generated by an image generator and including a first memory, a second memory, a selection circuit, a timing controller, and a display panel is provided. The first memory is configured to store first display data. The second memory is configured to store second display data. The second memory is disposed independent of the first memory. The selection circuit selects either the first display data or the second display data to serve as specific data based on a first selection signal. The timing controller generates the first selection signal according to the voltage level of a specific pin and provides the specific data to the image generator. The image generator generates the image data according to the specific data. The display panel displays an image based on the image data.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: November 30, 2021
    Assignee: ACER INCORPORATED
    Inventors: Yi-Chang Lai, Chih-Chiang Chen, Hsu-Hsiang Tseng, Chao-Shih Huang
  • Publication number: 20210366954
    Abstract: A semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure.
    Type: Application
    Filed: March 4, 2021
    Publication date: November 25, 2021
    Inventors: Yung-Hsiang CHEN, Yu-Lung YEH, Yen-Hsiu CHEN, Bo-Chang SU, Cheng-Hsien CHEN
  • Publication number: 20210366840
    Abstract: In some embodiments, the present application provides a method for manufacture a memory device. The method includes forming a multilayer stack including a first magnetic layer and a first dielectric layer and forming another magnetic layer. The multilayer stack and the another magnetic layer are tailored to meet dimensions of a package structure. The package structure includes a chip having a memory cell and an insulating material enveloping the chip, where an outer surface of the package structure comprises the insulating material. The tailored multilayer stack and the tailored another magnetic layer are attached to the outer surface of the package structure.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Kuo-An Liu, Chia-Hsiang Chen
  • Publication number: 20210365213
    Abstract: A memory device and a method for reducing read disturb errors of the memory device are provided. The memory device includes a plurality of memory cells arranged in series and organized into a plurality of blocks, a plurality of word lines respectively coupled to corresponding memory cells, and a controller coupled to the word lines for performing page read operations on the pages in respective blocks through corresponding word lines, in which each of the blocks comprises a plurality of pages of two or more types. The controller accumulates a page read count of the pages of each type in respective blocks, and arranges data to be stored according to the page read count and a latency factor corresponding to the pages of each type in each of the blocks.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Yen-Hsiang Chen, Nai-Ping Kuo
  • Publication number: 20210365729
    Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A second neural network for video stabilization is trained to generate stabilized HDR images in a time-dependent manner.
    Type: Application
    Filed: May 25, 2020
    Publication date: November 25, 2021
    Applicant: Novatek Microelectronics Corp.
    Inventors: Jen-Huan Hu, Wei-Ting Chen, Yu-Che Hsiao, Shih-Hsiang Lin, Po-Chin Hu, Yu-Tsung Hu, Pei-Yin Chen
  • Publication number: 20210367113
    Abstract: The display device includes a substrate, a patterned wall, the first, second, third sub-pixels, and an optical layer. The patterned wall is disposed on the substrate and has a plurality of openings. The first sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The second sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer. The third sub-pixel is disposed in one of the openings and includes a light-emitting element and a wavelength conversion layer, wherein a first distance between a top surface of the light-emitting element and a top surface of the patterned wall is about 10 um to about 100 um. The optical layer is disposed on the patterned wall and in direct contact with at least one of the first sub-pixel, the second sub-pixel, and the third sub-pixel.
    Type: Application
    Filed: May 21, 2020
    Publication date: November 25, 2021
    Inventors: Chih-Hao LIN, Hui-Ru WU, Jo-Hsiang CHEN, Jian-Chin LIANG, Ai-Sen LIU
  • Patent number: 11182533
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: November 23, 2021
    Inventors: Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen
  • Patent number: 11183503
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Chih-Hsiang Chang, Fu-Chen Chang
  • Patent number: 11184990
    Abstract: The present disclosure provides a fixing device for fixing an external electronic component on a motherboard in a chassis. The fixing device includes a fixing block and a telescopic block. The fixing block is fixed on the chassis. One end of the telescopic block is slidably mounted in the fixing block, the other end protrudes from the fixing block and holds the electronic component. A chassis including the above-described fixing device to hold electronic components of different sizes is also provided.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: November 23, 2021
    Assignee: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD.
    Inventors: Ching-Jou Chen, Tzu-Wei Lai, Wen-Hsiang Hung, Jun-Bo Yang, Chun-Bao Gu
  • Publication number: 20210358212
    Abstract: Techniques performed by a data processing system for reconstructing a three-dimensional (3D) model of the face of a human subject herein include obtaining source data comprising a two-dimensional (2D) image, three-dimensional (3D) image, or depth information representing a face of a human subject. Reconstructing the 3D model of the face also includes generating a 3D model of the face of the human subject based on the source data by analyzing the source data to produce a coarse 3D model of the face of the human subject, and refining the coarse 3D model through free form deformation to produce a fitted 3D model. The coarse 3D model may be a 3D Morphable Model (3DMM), and the coarse 3D model may be refined through free-form deformation in which the deformation of the mesh is limited by applying an as-rigid-as-possible (ARAP) deformation constraint.
    Type: Application
    Filed: July 15, 2020
    Publication date: November 18, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Noranart VESDAPUNT, Wenbin ZHU, Hsiang-Tao WU, Zeyu CHEN, Baoyuan WANG