Patents by Inventor Hsiang Chen

Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11842676
    Abstract: An electronic device is provided. The electronic device includes a detection circuit. The detection circuit includes a programming detection circuit, a light-emitting detection circuit and a determining circuit. The programming detection circuit receives a scan signal, a reset signal and a light-emitting enable signal for a driving circuit of a pixel unit, and provides a first detection signal in a first stage according to the scan signal, the reset signal and the light-emitting enable signal. The light-emitting detection circuit receives the scan signal, the reset signal and the light-emitting enable signal, and provides a second detection signal in a second stage according to the scan signal, the reset signal and the light-emitting enable signal. The determining circuit determines whether to output the light-emitting enable signal to the driving circuit according to the first detection signal and the second detection signal.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: December 12, 2023
    Assignee: Innolux Corporation
    Inventors: Yong-Zhi Liu, Ming-Chun Tseng, Kung-Chen Kuo, Lien-Hsiang Chen, Po-Syun Chen
  • Publication number: 20230391806
    Abstract: A phosphorus-containing compound of Formula (1) and a preparation method thereof are provided. The phosphorus-containing compound is a compound having a reactive functional group and containing a phosphorus atom in its structure. The preparation method includes: (1) reacting magnolol and phosphoryl chloride in a first alkaline environment to obtain an intermediate product; and (2) reacting the intermediate product and a benzenediol in a second alkaline environment to obtain the phosphorus-containing compound.
    Type: Application
    Filed: May 23, 2023
    Publication date: December 7, 2023
    Inventors: Chien-Hsiang CHEN, Chun-Hsiung CHANG
  • Patent number: 11836295
    Abstract: A free space input standard is instantiated on a processor. Free space input is sensed and communicated to the processor. If the free space input satisfies the free space input standard, a touch screen input response is invoked in an operating system. The free space input may be sensed using continuous implicit, discrete implicit, active explicit, or passive explicit approaches. The touch screen input response may be invoked through communicating virtual touch screen input, a virtual input event, or a virtual command to or within the operating system. In this manner free space gestures may control existing touch screen interfaces and devices, without modifying those interfaces and devices directly to accept free space gestures.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: December 5, 2023
    Assignee: West Texas Technology Partners, LLC
    Inventors: Shashwat Kandadai, Nathan Abercrombie, Yu-Hsiang Chen, Sleiman Itani
  • Patent number: 11835866
    Abstract: A method includes: providing a workpiece to a semiconductor apparatus, the workpiece including a material layer, wherein the material layer includes a first strip having a first plurality of exposure fields configured to be exposed in a first direction and a second plurality of exposure fields configured to be exposed in a second direction different from the first direction; scanning the first strip along a first scan route in the first direction to generate first topography measurement data; scanning the first strip along a second scan route in the second direction to generate second topography measurement data; and exposing the first plurality of exposure fields according to the first topography measurement data and exposing the second plurality of exposure fields according to the second topography measurement data.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Yao Lee, Yeh-Chin Wang, Yang-Ann Chu, Yung-Hsiang Chen, Yung-Cheng Chen
  • Patent number: 11837312
    Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: December 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsiang Chen, Chih-Yang Chang, Chia Yu Wang, Meng-Chun Shih
  • Patent number: 11829549
    Abstract: A method of controlling a stylus pen of a touch panel includes steps of: outputting an uplink control signal to a sensing electrode of the touch panel for controlling the stylus pen in an uplink control period; and outputting a direct-current (DC) voltage to a gate line of the touch panel in the uplink control period.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: November 28, 2023
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Hung-Hsiang Chen, Wei-Kai Chen, Huang-Chin Tang
  • Publication number: 20230378244
    Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a plurality of isolation regions on a semiconductor substrate, forming a protective layer in a resistor region of the semiconductor substrate, after forming the protective layer, etching a gate dielectric layer to form first and second gate dielectric layers of a transistor in a transistor region of the semiconductor substrate, removing the protective layer, forming first and second dummy gate stacks over the first and second gate dielectric layers, respectively, forming a resistor in the resistor region, forming third and fourth dummy gate stacks over the resistor, and replacing each of the first, second, third, and fourth dummy gate stacks with a conductive material.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: Liang-Hsiang Chen, Chinyu Su, Che-Chih Hsu
  • Publication number: 20230378169
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, a first gate electrode, a second gate electrode, a first doped region, a second doped region, a third doped region, and a first interconnection structure. The substrate comprises a well region of a first conductive type. The first and second gate electrodes are disposed on the substrate. The first, second, and third doped regions are embedded within the well region and are of the first conductive type. The first interconnection structure electrically connects the first gate electrode and the second gate electrode. The first doped region and the second doped region are disposed on opposite sides of the first gate electrode.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 23, 2023
    Inventors: HO-HSIANG CHEN, CHI-HSIEN LIN, YING-TA LU, HSIEN-YUAN LIAO, HSIU-WEN WU, CHIAO-HAN LEE, TZU-JIN YEH
  • Publication number: 20230372640
    Abstract: A nebulizer (1) includes a host (10) and a nozzle tube (20). The host includes a main body (11), a control module (12) and a sensor (13). The nozzle tube (20) includes a tube (21), a nozzle (22) and a detecting structure (23). The tube (21) includes a chamber (210). The nozzle (22) is arranged on one side of the tube (21) and communicates with the chamber (210). The detecting structure (23) includes a shutter (231) and a swinging member (232) connected with the shutter (231). The shutter (231) is disposed corresponding to the position of the sensor (13). The air blown from the nozzle (22) flows into the tube (21) and blows the swinging member (232) to drive the shutter (231) to activate the sensor (13).
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: Po-Chang CHEN, Hsin-Chen WANG, Chia-Chin YANG, Hao-Hsiang CHEN, Chun-Wei HSU
  • Publication number: 20230378910
    Abstract: A band-pass filter (BPF) includes first and second windings. The first winding includes first and second terminals, a first outer extending portion extending from the first terminal, a second outer extending portion extending from the second terminal, and a first conductive structure configured to electrically connect the first and second outer extending portions to each other at a location opposite the first and second terminals. The second winding includes third and fourth terminals positioned between the first and second terminals, and a second conductive structure electrically connected to the third and fourth terminals and extending between the first conductive structure and each of the first and second outer extending portions.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Publication number: 20230369425
    Abstract: a transistor and an interconnect structure disposed over the transistor. The interconnect structure includes a first dielectric layer, a first conductive feature in the first dielectric layer, a first etch stop layer (ESL) disposed over the first dielectric layer and the first conductive feature, a dielectric feature disposed in the first ESL, an electrode disposed over the dielectric feature, and a second ESL disposed on the first ESL and the electrode.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Yu-Hsiang Chen, Po-Hsiang Huang, Wen-Sheh Huang, Hsing-Leo Tsai, Chia-En Huang
  • Publication number: 20230369431
    Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes: a substrate; a gate trench located in the substrate; a gate oxide layer located on a side wall and a bottom of the gate trench; and a gate conductive layer located on a surface of the gate oxide layer, a top of the gate conductive layer being lower than a top of the gate trench. The gate oxide layer includes an ion implantation area. A bottom of the ion implantation area is higher than a bottom of the gate conductive layer and lower than the top of the gate conductive layer, and a top of the ion implantation area is higher than or flush with the top of the gate conductive layer.
    Type: Application
    Filed: August 24, 2022
    Publication date: November 16, 2023
    Inventors: WEI CHANG, CHUN-HSIANG CHEN, Zhaohong LV, Yongchang ZHUO, TIEH-CHIANG WU
  • Patent number: 11818875
    Abstract: A method for forming a memory includes: providing a substrate, a plurality of discrete bit line structures being located on the substrate, and an area surrounded by the adjacent bit line structures and the substrate and having a central axis; forming, on the substrate, a first conductive film filling an area between the adjacent bit line structures; etching the first conductive film by a first etching process to form a first conductive layer; forming a second conductive film on the top surface of the first conductive layer; and etching the second conductive film and the first conductive layer by a second etching process, the remaining second conductive film and the first conductive layer forming a capacitive contact window.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: November 14, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xiao Zhu, Yi-Hsiang Chen, Lihui Yang, Hung-I Lin, Yun-Chieh Mi, Jinfeng Gong
  • Patent number: 11817385
    Abstract: An integrated circuit includes an inductor that includes a first set of conductive lines in a first metal layer, and is over a substrate, and a guard ring. The guard ring includes a first conductive line in a second metal layer, and extending in a first direction, a second conductive line extending in a second direction, and a first staggered line coupled between the first conductive line and the second conductive line. The first staggered line includes a second set of conductive lines in the second metal layer, and extends in the first direction, a third set of conductive lines in a third metal layer, and extends in the second direction, and a first set of vias coupling the second and third set of conductive lines together. All metal lines in the third metal layer that are part of the guard ring extend in the second direction.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiao-Han Lee, Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 11814743
    Abstract: A plating membrane includes a support structure extending radially outward from a nozzle that is to direct a flow of a plating solution toward a wafer. The plating membrane also includes a frame, supported by the support structure, having an inner wall that is angled outward from the nozzle. The outward angle of the inner wall relative to the nozzle directs a flow of plating solution from the nozzle in a manner that increases uniformity of the flow of the plating solution toward the wafer, reduces the amount of plating solution that is redirected inward toward the center of the plating membrane, reduces plating material voids in trenches of the wafer (e.g., high aspect ratio trenches), and/or the like.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Hsiang Chen, Hung-San Lu, Ting-Ying Wu, Chuang Chihchous, Yu-Lung Yeh
  • Publication number: 20230361050
    Abstract: A package structure includes a mounting pad having a mounting surface; a semiconductor chip having a magnetic device, a first magnetic field shielding, and a molding. The semiconductor chip comprises a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface, wherein the second surface is attached to the mounting surface of the mounting pad, and a third surface connecting the first surface and the second surface. The first magnetic field shielding including a plurality of segments laterally at least partially surrounding the semiconductor chip, wherein a bottom surface of the first magnetic field shielding is attached to the mounting surface of the mounting pad, wherein the mounting surface comprises first portion free from overlapping with the first magnetic field shielding from a top view perspective. The molding surrounding the mounting pad and in direct contact with the mounting surface.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Inventors: HARRY-HAK-LAY CHUANG, CHIA-HSIANG CHEN, MENG-CHUN SHIH, CHING-HUANG WANG, TIEN-WEI CHIANG
  • Publication number: 20230356354
    Abstract: Exemplary carrier heads for a chemical mechanical polishing apparatus may include a carrier body. The carrier heads may include a substrate mounting surface coupled with the carrier body. The carrier heads may include an inner ring that is sized and shaped to circumferentially surround a peripheral edge of a substrate positioned against the substrate mounting surface. The inner ring may be characterized by a first end having a first surface that faces the carrier body and a second end having a second surface opposite the first surface. The second end of the inner ring may be radially displaceable. The carrier heads may include an outer ring having an inner surface that is disposed against an outer surface of the inner ring.
    Type: Application
    Filed: May 3, 2022
    Publication date: November 9, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Jeonghoon Oh, Andrew Nagengast, Steven M. Zuniga, Eric L. Lau, Hari Prasath Rajendran, Satish Radhakrishnan, Kuen-Hsiang Chen, Ekaterina A. Mikhaylichenko
  • Patent number: 11810300
    Abstract: This application provides a method for detecting images of testing object using hyperspectral imaging. Firstly, obtaining a hyperspectral imaging information according to a reference image, hereby, obtaining corresponded hyperspectral image from an input image and obtaining corresponded feature values for operating Principal components analysis to simplify feature values. Then, obtaining feature images by Convolution kernel, and then positioning an image of an object under detected by a default box and a boundary box from the feature image. By Comparing with the esophageal cancer sample image, the image of the object under detected is classifying to an esophageal cancer image or a non-esophageal cancer image. Thus, detecting an input image from the image capturing device by the convolutional neural network to judge if the input image is the esophageal cancer image for helping the doctor to interpret the image of the object under detected.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: November 7, 2023
    Assignee: National Chung Cheng University
    Inventors: Hsiang-Chen Wang, Tsung-Yu Yang, Yu-Sheng Chi, Ting-Chun Men
  • Patent number: 11809227
    Abstract: An electronic device is provided. The electronic device includes a function module, a casing, and a cover. The casing includes a space to accommodate the function module. The cover includes a frame and an extending portion. The frame covers the casing. The extending portion extends outward from a sidewall of the frame to protrude from the casing, and the extending portion and the frame are integrally formed.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: November 7, 2023
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Yi-Chen Yen, Yung-Hsiang Chen, Hsi-Tan Huang
  • Publication number: 20230349734
    Abstract: There is provided a transducer structure having at least one mechanical restraint. The at least one mechanical restraint is shaped to receive a transducer such that the at least one mechanical restraint at least partially limits the positioning of the transducer on the transducer structure. The at least one mechanical restraint pins at least a portion of the transducer in at least two degrees of freedom when the transducer is positioned on the transducer structure.
    Type: Application
    Filed: April 13, 2023
    Publication date: November 2, 2023
    Inventors: Samuel Joonsik Kim, I-Hsiang Chen, Robert Joseph Brooks