Abstract: A communication circuit arrangement includes a signal path circuit to estimate, using a first kernel dimension filter and a first delay tap dimension filter, a first interference signal produced by a first amplifier. The signal path circuit further estimates, using a second kernel dimension filter and a second delay tap dimension filter, a second interference signal produced by a second amplifier. A cancellation circuit of the communication circuit arrangement may subtract a combination of the first interference signal and the second interference signal from a received signal to obtain a filtered signal, and one or more filter adaptation circuits may alternate between a kernel update phase and a delay update phase to update the first kernel dimension filter and the second kernel dimension filter during the kernel update phase, and update the first delay tap dimension filter and the second delay tap dimension filter during the delay update phase.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure also includes a first conductive feature and a second conductive feature surrounded by the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element having a first portion over the second dielectric layer and a second portion penetrating through the second dielectric layer to be electrically connected to the first conductive feature. In addition, the semiconductor device structure includes a conductive via penetrating through the second dielectric layer to be electrically connected to the second conductive feature. The second portion of the resistive element is wider than the conductive via.

Abstract: A transistor and an interconnect structure disposed over the transistor. The interconnect structure includes a first dielectric layer, a first conductive feature in the first dielectric layer, a first etch stop layer (ESL) disposed over the first dielectric layer and the first conductive feature, a dielectric feature disposed in the first ESL, an electrode disposed over the dielectric feature, and a second ESL disposed on the first ESL and the electrode.

Abstract: A coffee grinder including a base and a grinding component is provided. The base includes a body part, a first assembly part, and a second assembly part. The first assembly part and the second assembly part are connected to the body part and protrude from one side of the body part. The first assembly part is disposed above the second assembly part and includes a drive shaft. One end of the drive shaft faces the second assembly part. The grinding component includes an outer burr module and an inner burr shaft assembled in the outer burr module. A side surface of the outer burr module is assembled to the second assembly part. The drive shaft of the first assembly part is assembled with one end of the inner burr shaft. One end of the drive shaft drives the inner burr shaft to rotate relative to the outer burr module.

Abstract: An electronic window is provided for adjusting light and includes a first panel, a second panel, and an intermediate layer. The first panel includes a first alignment layer. The second panel includes a second alignment layer. The intermediate layer is disposed between the first panel and the second panel. The angle of orientation of the first alignment layer is between 25 degrees and 65 degrees, and the angle of orientation of the second alignment layer is between 115 degrees and 155 degrees.

Abstract: A display device includes: a substrate; a metal layer disposed on the substrate; an insulating layer disposed on the metal layer; and a first light emitting diode including a first electrode disposed on the metal layer, wherein a via hole passes through the insulating layer, the first electrode electrically connects to the metal layer through the via hole, and an outline of the via hole includes an arc edge.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first dielectric layer and a first conductive feature and a second conductive feature surrounded by the first dielectric layer. The semiconductor device structure also includes a second dielectric layer over the first dielectric layer and a resistive element electrically connected to the first conductive feature. The second dielectric layer surrounds a portion of the resistive element. The semiconductor device structure further includes a conductive via electrically connected to the second conductive feature. The second dielectric layer surrounds a portion of the conductive via, and a contact area between the resistive element and the first conductive feature is wider than a contact area between the conductive via and the second conductive feature.

Abstract: A Lamb wave resonator includes a piezoelectric material layer, a first finger electrode, a second finger electrode, at least two floating electrodes, and at least two gaps. The first finger electrode is disposed on one side of the piezoelectric material layer and includes a first main portion and first fingers. The second finger electrode is disposed on the side of the piezoelectric material layer and includes a second main portion and second fingers. The first fingers are parallel to and alternately arranged with the second fingers. The floating electrodes are disposed between each first finger and each second finger, and the gaps are disposed at two ends of each floating electrode, respectively.

Abstract: The disclosure provides an electronic device including a pixel circuit and a protection circuit. The pixel circuit includes a driving transistor. The protection circuit includes a first connection transistor, a first switching transistor, and a logic circuit. The first connection transistor is coupled to the driving transistor. The first switching transistor is coupled to the first connection transistor. The logic circuit is coupled to the first switching transistor. The electronic device of the disclosure may provide a pixel protection function through the protection circuit coupled with the pixel circuit.

Abstract: In some embodiments, the present application provides an integrated chip. The integrated chip includes a chip comprising a semiconductor device. A shielding structure abuts the chip. The shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip. The first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers. The first dielectric layer is disposed between the two or more metal layers.

Abstract: A pixel array package structure includes: a substrate; a pixel array disposed on the substrate, in which the pixel array includes a plurality of light emitting diode chips, and the light emitting diode chips include at least one red diode chip, at least one green diode chip, at least one blue diode chip, and a combination thereof; a reflective layer disposed on the substrate and between any two adjacent of the light emitting diode chips; a light-absorbing layer disposed on the reflective layer and surrounding the pixel array; and a light-transmitting layer disposed on the pixel array, the reflective layer, and the light-absorbing layer, in which the light-transmitting layer has an upper surface and a lower surface opposite thereto, and the lower surface is in contact with the pixel array, and the upper surface has a roughness of 0.005 mm to 0.1 mm.

Abstract: An oscillator includes a forward stage including first and second terminals and a transformer-coupled band-pass filter (BPF) coupled between the first and second terminals and including a coupling device between the first and second terminals, and a transformer including first and second windings in a metal layer of an IC. The first winding includes a first conductive structure coupled to the first terminal and a second conductive structure coupled to a voltage node, a third conductive structure including first and second extending portions connected to the first and second conductive structures. The second winding includes a fourth conductive structure including a third extending portion coupled to the voltage node, and a fourth extending portion coupled to the second terminal. The third extending portion is between the second conductive structure and the first extending portion, and the fourth extending portion is between the first conductive structure and the second extending portion.

Abstract: A backlight module includes a light guide element including first optical microstructures and second optical microstructures. An angle value of an angle of the first optical microstructures is V1. When the second optical microstructures are respectively recessed into or protrude from a bottom surface, a projection of each sub-optical microstructure on a reference plane has a peak point closest or to farthest from a light emitting surface and a first valley point and a second valley point farthest from or closest to the light emitting surface, a height difference between the peak point and the first valley point or the second valley point is ?H, a length difference between the peak point and the first valley point or the second valley point is ?L, and tan?1(?H/?L) is V2, where V2>0 and V2?0.5·V1.

Abstract: a first dielectric layer, a first conductive feature and a second conductive feature in the first dielectric layer, a first dielectric feature disposed directly on the first conductive feature; a first etch stop layer (ESL) disposed over the first dielectric layer and the second conductive feature, a first conductive layer disposed on and in contact with the first dielectric feature, a second ESL disposed over the first conductive layer, a second dielectric layer disposed directly on the first ESL and the second ESL, a first via extending through the second dielectric layer and the second ESL to contact with the first conductive feature, and a second via extending through the second dielectric layer and the first ESL to contact with the second conductive feature.

Abstract: A method for recognizing arteries and veins on a fundus image includes: executing a pre-process operation on the fundus image, so as to obtain a pre-processed fundus image; generating a fundus spectral reflection dataset associated with pixels of the pre-processed fundus image, based on the pre-processed fundus image, and a spectral transformation matrix; obtaining a plurality of principle component scores associated with the pixels of the pre-processed fundus image, respectively; and determining, for each of the pixels of the pre-processed fundus image that has been determined as a part of a blood vessel, whether the pixel belongs to a part of an artery or a part of a vein.

Abstract: A structure of transferring dies includes an oxide layer supporting feature, multiple dies, a bonding feature, a supporting wafer, and a spacer. The oxide layer supporting feature includes multiple repeating units. Each repeating unit has a die setting region and a peripheral region. The die setting region of one repeating unit is separated from the peripheral region of another adjacent repeating unit. The die is disposed on the die setting region and the bonding feature is disposed on the peripheral region of the oxide layer supporting feature. The supporting wafer is disposed under the oxide layer supporting feature and separated from the die and the bonding feature by a gap. The spacer is disposed between the bonding feature and the supporting wafer, and bonded to the bonding feature.

Abstract: A video conference device may include at least one camera, at least one processor, and an interface. The at least one camera may be arranged to capture an image of a scene. The at least one processor may be arranged to: if a trigger occurs, detect a display region in the image based on a location of a pattern in the image, wherein in response to the display region being detected, the display region is excluded from the image; detect at least one specific object in the image; and extract the at least one detected specific object in the image as at least one local image. The interface may be arranged to transmit the at least one local image.

Abstract: A free space input standard is instantiated on a processor. Free space input is sensed and communicated to the processor. If the free space input satisfies the free space input standard, a touch screen input response is invoked in an operating system. The free space input may be sensed using continuous implicit, discrete implicit, active explicit, or passive explicit approaches. The touch screen input response may be invoked through communicating virtual touch screen input, a virtual input event, or a virtual command to or within the operating system. in this manner free space gestures may control existing touch screen interfaces and devices, without modifying those interfaces and devices directly to accept free space gestures.

Abstract: A method of verifying an integrated circuit stack includes adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate. The method further includes converting the first dummy layer location to the connecting substrate. The method further includes adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad. The method further includes performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.

Abstract: A biosensing chip is provided, including a substrate having a photoelectric conversion material, and an electrode disposed on the substrate and including two contact portions and an electrode pattern, wherein the photoelectric conversion material is a monocrystalline silicon material, and the electrode pattern includes micro-electrodes in the form of interdigitated sawtooth. The biosensing chip and the method using the same may distinguish a lesion site of cancer cells and the degree of cancer lesions.