Abstract: Briefly, embodiments, such as methods, systems and/or circuits for controlling a power signal to be supplied to a processing device. In one aspect, a magnitude of a power supplied to a processing device may be changed based, at least in part on an estimated and/or predicted load.

Abstract: An ultrasonic transducer device includes a first electrode, an insulating layer, an oscillating membrane, a second electrode, and a third electrode. The insulating layer is disposed on the first electrode. The oscillating membrane is disposed over the insulating layer. A cavity is between the oscillating membrane and the insulating layer. The second electrode is disposed on the oscillating membrane. The third electrode is disposed in the cavity and has a plurality of first electrode openings overlapping the second electrode. The second electrode and the third electrode are each located at different sides of the oscillating membrane.

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.

Abstract: A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction; dividing the integrated circuit into a plurality of grid units, wherein he first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units; estimating a first thermal conductivity of each of the first subsets of grid units; estimating a second thermal conductivity of each of the second subsets of grid units; and estimating an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.

Abstract: A semiconductor structure includes a semiconductor die containing an array of first bonding structures. Each of the first bonding structures includes a first metal pad located within a dielectric material layer and a basin-shaped underbump metallization (UBM) pad located within a respective opening in a passivation dielectric layer and contacting the first metal pad. An interposer includes an array of second bonding structures, wherein each of the second bonding structures includes an underbump metallization (UBM) pillar having a respective cylindrical shape. The semiconductor die is bonded to the interposer through an array of solder material portions that are bonded to a respective one of the first-type bonding structures and to a respective one of the second-type bonding structures.

Abstract: A semiconductor device includes a memory array. The memory array is configured to calculate first data and second data, and includes a first memory cell and a second memory cell. The first memory cell is configured to generate a first current signal at a first node, in response to the first data. The second memory cell is configured to generate a second current signal at the first node when the first memory cell generating the first current signal, in response to the second data. When the first data has a first data value and the second data has a second data value, the second memory cell is further configured cancel the first current signal with the second current signal. The second data value is a negative value of the first data value.

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure includes forming a stack of channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shape structure, forming a dummy gate stack over a channel region of the fin-shape structure, recessing a source/drain region to form a source/drain trench, forming an epitaxial feature in the source/drain trench, after the forming of the epitaxial feature removing the dummy gate stack, releasing the channel layers in the channel region as channel members, forming a gate structure wrapping around each of the channel members, and after the forming of the gate structure performing an ion implantation to increase a dopant concentration of a dopant in the epitaxial feature.

Abstract: A reference current generating circuit includes a temperature sensing circuit, an adjustable resistor, a current mirror, and a calibration circuit. The temperature sensing circuit senses a temperature of the reference current generating circuit to provide a voltage. The adjustable resistor generates a reference current according to the voltage. The current mirror generates an output current according to the reference current. The calibration circuit includes a resistor, a comparator and a control circuit. The resistor generates an output voltage according to the output current. The comparator compares the output voltage with a reference voltage to generate a comparison result. The control circuit sequentially generates and transmits multiple control signals to the adjustable resistor, and determines a final control signal according to the comparison result.

Abstract: An interconnect structure according to the present disclosure includes a first dielectric layer, a first conductive feature and a second conductive feature in the first dielectric layer, a first dielectric feature disposed directly on the first conductive feature; a first etch stop layer (ESL) disposed over the first dielectric layer and the second conductive feature, a first conductive layer disposed on and in contact with the first dielectric feature, a second ESL disposed over the first conductive layer, a second dielectric layer disposed directly on the first ESL and the second ESL, a first via extending through the second dielectric layer and the second ESL to contact with the first conductive feature, and a second via extending through the second dielectric layer and the first ESL to contact with the second conductive feature.

Abstract: A method of making a semiconductor device includes electrically connecting a component to a first side of a first fuse, wherein the first fuse is a first distance from the component. The method further includes electrically connecting the component to a first side of a second fuse, wherein the second fuse is a second distance from the component, and the second distance is different than the first distance. The method further includes electrically connecting a second side of the second fuse to a dummy vertical interconnect segment.

Abstract: Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.

Abstract: An encapsulation structure is provided. The encapsulation structure includes a flexible substrate that has an element area and a non-element area. The encapsulation structure also includes multiple electronic elements disposed in the element area. The encapsulation structure further includes multiple light-guiding structures disposed on the electronic elements. The light-guiding structure includes a convex structure and/or a concave structure. The convex structure, in a cross-section, has at least one curved surface, at least two inclined surfaces, or a combination of at least one curved surface and one inclined surface. The concave structure, in a cross-section, has at least one curved surface or at least two inclined surfaces.

Abstract: A method for forming a semiconductor device structure is provided. The method includes removing a portion of a dielectric layer to form a trench in the dielectric layer. The method includes forming a barrier layer in the trench. The method includes forming a seed layer in the trench and over the barrier layer. The seed layer is doped with manganese. The method includes annealing the seed layer in a first process gas including a first hydrogen gas. A volume ratio of the first hydrogen gas to the first process gas ranges from about 50% to about 100%, and the manganese diffuses from the seed layer to the barrier layer during the annealing of the seed layer in the first process gas.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes forming a dielectric layer over a portion of a substrate, forming an aluminum-containing work function layer over the dielectric layer, where a concentration of aluminum in a first portion of the aluminum-containing work function layer is different than the concentration of aluminum in a second portion of the aluminum-containing work function layer, and forming a metal layer over the aluminum-containing work function layer.

Abstract: Disclosed is an adjustable respiratory system of concentration—modulable hydrogen-oxygen ventilator, including: a supplying hydrogen-oxygen mixed gas auxiliary device, a pure water electrolysis hydrogen-oxygen generator including an ion exchange membrane, an oxidation catalyst layer and a reduction catalyst layer; a pair of diffusive metallic layers; an anode conductively connected to the anode metallic layer, and a cathode conductively connected to the cathode metallic layer; a sealed accommodation body being provided with a water inlet, a hydrogen hole, and an oxygen hole; a humidifier bottle including an oxygen delivery tube distal from the oxygen hole, a hydrogen delivery tube distal from the hydrogen hole being respectively inserted into the clean water in humidifier, and a hydrogen-oxygen mixed gas output tube. A hydrogen concentration detector inside or outside the ventilator provides alert and safety for the users and facilities.

Abstract: A high-pressure labor-saving pressure regulator includes a main body, valve core assembly, main piston assembly, balance piston, and pressure regulating handle. The inside of the main body has a pressure reducing space, an input channel, and an output channel. The pressure reducing space includes a first subspace and a second subspace communicated by a seat port. The valve core member is used to regulate an opening of the seat port, and two ends of a poppet spring are respectively abutted against the valve core member and the main body. The main piston assembly includes a piston rod, a main piston, and a pressure regulating spring. A space between a bottom surface of the main piston and the main body, and a space between a top surface of the balance piston and the main body, allows fluid to flow into the top surface of the balance piston.

Abstract: A three dimensional (3D) Integrated Circuit (IC) package is provided. The 3D IC package includes a first IC die having a first substrate at a back side of the first IC die and a second IC die stacked at the back side of the first IC die and facing the first substrate. The 3D IC further includes a Through Silicon Via (TSV) through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV. A protection module is fabricated in the first substrate. The protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

Abstract: A transparent projection film structure is provided. The transparent projection film structure includes a base layer and a patterned light-guiding layer disposed on the base layer. In a cross-sectional view, the patterned light-guiding layer has light-guiding units, and hollow areas are formed between the light-guiding units. The transparent projection film structure also includes a scattering layer disposed on the base layer and includes scattering particles. At least some of the scattering particles correspond to the patterned light-guiding layer.

Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.