Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.

Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

Abstract: A method for manufacturing a golf ball having a multi-layered pattern is provided. Firstly, a semi-finished product of the golf ball is provided and includes a ball-shaped body and a base layer covering an outer surface of the ball-shaped body. Then, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball by spraying from each of an upper position, a middle position, and a lower position. The multi-layered pattern includes an upper-layer pattern area, a mid-layer pattern area, and a lower-layer pattern area that are different in color from each other.

Abstract: An out-of-order buffer includes an out-of-order queue and a controlling circuit. The out-of-order queue includes a request sequence table and a request storage device. The controlling circuit receives and temporarily stores the plural requests into the out-of-order queue. After the plural requests are transmitted to plural corresponding target devices, the controlling circuit retires the plural requests. The request sequence table contains m×n indicating units. The request sequence table contains m entry indicating rows. Each of the m entry indicating rows contains n indicating units. The request storage device includes m storage units corresponding to the m entry indicating rows in the request sequence table. The state of indicating whether one request is stored in the corresponding storage unit of the m storage units is recoded in the request sequence table. The storage sequence of the plural requests is recoded in the request sequence table.

Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.

Abstract: An electrical connection assembly includes two electrical connectors and a bridge connector. Each of the two electrical connectors includes plural terminals and an insulation housing that accommodates the terminals. The bridge connector is located between the two electrical connectors. The bridge connector includes an insulation body, a conductive plastic, plural signal terminals, and plural ground terminals. The conductive plastic is covered by the insulation body. The ground terminals and the signal terminals of the bridge connector are arranged at intervals. The ground terminals of the bridge connector are in electrical contact with the conductive plastic. When two opposite sides of the insulation body are respectively coupled to the two electrical connectors so as to be surrounded by the two electrical connectors, the ground terminals of the bridge connector are respectively in electrical contact with the ground terminals of the two electrical connectors.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

Abstract: A motherboard includes a circuit board and a connector mounted on the circuit board. The connector comprises a socket and a latch pivotally mounted on one end of the socket. The latch comprises a body, a pressing member connected to one side of the body and extending outward from one side of the body to the outside of the socket, exposing an area from a side of the interface card for finger pressing. The supporting member is connected to another side of the body, and when the pressing member is pressed, it drives the body to pivot and causes the pushing portion to lift the interface card, and the supporting member stop the body from pivoting by resting against the circuit board.

Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

Abstract: An antenna module includes first to third radiators and a ground radiator. The first radiator includes first and second sections and excites at a first frequency band. An extension direction of the first section, including a feeding end, is not parallel to an extension direction of the second section. The second radiator includes third and fourth sections. The third section extends from an intersection of the first and second sections. The third section excites at a second frequency band. The third radiator is disposed beside the first radiator and away from the second radiator. The ground radiator is disposed on one side of the first, second, and third radiators, and includes a ground end. The fourth section of the second radiator is connected to the third section and the ground radiator. The third radiator is connected to the ground end.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: A Totem Pole PFC circuit includes at least one fast-switching leg, a slow-switching leg, and a control unit. Each fast-switching leg includes a fast-switching upper switch and a fast-switching lower switch. The slow-switching leg is coupled in parallel to the at least one fast-switching leg, and the slow-switching leg includes a slow-switching upper switch and a slow-switching lower switch. The control unit receives an AC voltage with a phase angle, and the control unit includes a current detection loop, a voltage detection loop, and a control loop. The control loop generates a second control signal assembly to respectively control the slow-switching upper switch and the slow-switching lower switch. The control loop controls the second control signal assembly to follow the phase angle, and dynamically adjusts a duty cycle of the second control signal assembly to turn on or turn off the slow-switching upper switch and the slow-switching lower switch.

Abstract: An electrical connector is configured to couple to a butt plug. The electrical connector includes an insulation body, plural signal terminals, plural ground terminals, and at least one conductive plastic. The insulation body has a tongue portion. The signal terminals are located in the insulation body. The ground terminals are located in the insulation body, and the ground terminals and the signal terminals are arranged at intervals. The conductive plastic is located on the tongue portion of the insulation body and is disposed along the tongue portion. When the tongue portion of the insulation body is coupled to the butt plug so as to be surrounded by the butt plug, plural ground terminals of the butt plug are in electrical contact with the conductive plastic.

Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.

Abstract: An electrical connector is configured to couple to a butt plug. The electrical connector includes an insulation body, plural signal terminals, plural ground terminals, and at least one conductive plastic. The insulation body has an accommodating recess. The signal terminals are located in the accommodating recess. The ground terminals are located in the accommodating recess, and the ground terminals and the signal terminals are arranged at intervals. The conductive plastic is located on a top surface of the insulation body facing the butt plug. When the butt plug is inserted into the accommodating recess of the insulation body, plural ground terminals of the butt plug are in electrical contact with the conductive plastic.

Abstract: Certain aspects of the present disclosure provide techniques for handling collisions between multiple universal subscriber identity module (MUSIM) gaps and measurement gaps (MGs) or other MUSIM gaps. In an exemplary method, a user equipment (UE) detects a collision between a first multiple universal subscriber identity module (MUSIM) gap occasion and at least one of a second MUSIM gap occasion or a measurement gap (MG) occasion; and processes signals in at least one of the first MUSIM gap occasion, the second MUSIM gap occasion, a third MUSIM gap occasion, or the MG occasion based on relative priorities of the first MUSIM gap occasion, the second MUSIM gap occasion, or the MG occasion.

Abstract: Aspects described herein relate to receiving, from a network node, an indication of information related to a configuration, including at least one of a modulation and coding scheme (MCS), a physical downlink shared channel (PDSCH) duration, a scrambling sequence, or a reference signal location, used for transmitting downlink signals to one or more co-scheduled UEs, receiving, from the network node, a downlink signal intended for the UE, wherein the signal is interfered by one or more interference signals transmitted to the one or more co-scheduled UEs, and removing, based on the indication, the one or more interference signals from the downlink signal. Other aspects relate to transmitting the information and downlink signals.

Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.

Abstract: An image object classification method and system are disclosed. The method is executed by a processor coupled to a memory. The method includes: providing an image file including at least one image object, performing a process of extracting multiple binary-classified characteristics on the image object to obtain a plurality of first results independent of each other in categories, combining the plurality of first results in a manner of dimensionality reduction based on concatenation, performing a process of characteristics abstraction on the combined first results to obtain a second result, and performing a process of characteristics integration on the plurality of first results and the second result in a manner of dot product of matrices to obtain a classification result.