Patents by Inventor Hsiang Huang

Hsiang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240126559
    Abstract: The present invention discloses a processor control method including: controlling a processor to execute a first operating system in a first state; when the processor executing the first operating system satisfies a predetermined condition, controlling the processor to switch from the first state to a second state; and controlling the processor to execute a second operating system in the second state, wherein an authority of the first state is higher than an authority of the second state.
    Type: Application
    Filed: March 15, 2023
    Publication date: April 18, 2024
    Inventors: Cheng-Chi HUANG, Shu-Cheng CHOU, Yu-Hsiang LIN
  • Publication number: 20240120639
    Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.
    Type: Application
    Filed: August 10, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hsiang Huang, Fong-Yuan Chang, Tsui-Ping Wang, Yi-Shin Chu
  • Patent number: 11955707
    Abstract: An antenna module includes first to third radiators and a ground radiator. The first radiator includes first and second sections and excites at a first frequency band. An extension direction of the first section, including a feeding end, is not parallel to an extension direction of the second section. The second radiator includes third and fourth sections. The third section extends from an intersection of the first and second sections. The third section excites at a second frequency band. The third radiator is disposed beside the first radiator and away from the second radiator. The ground radiator is disposed on one side of the first, second, and third radiators, and includes a ground end. The fourth section of the second radiator is connected to the third section and the ground radiator. The third radiator is connected to the ground end.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: April 9, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Chao-Hsu Wu, Hau Yuen Tan, Chien-Yi Wu, Shih-Keng Huang, Cheng-Hsiung Wu, Ching-Hsiang Ko
  • Patent number: 11955547
    Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: 11955338
    Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
  • Publication number: 20240113475
    Abstract: An electrical connector is configured to couple to a butt plug. The electrical connector includes an insulation body, plural signal terminals, plural ground terminals, and at least one conductive plastic. The insulation body has a tongue portion. The signal terminals are located in the insulation body. The ground terminals are located in the insulation body, and the ground terminals and the signal terminals are arranged at intervals. The conductive plastic is located on the tongue portion of the insulation body and is disposed along the tongue portion. When the tongue portion of the insulation body is coupled to the butt plug so as to be surrounded by the butt plug, plural ground terminals of the butt plug are in electrical contact with the conductive plastic.
    Type: Application
    Filed: February 2, 2023
    Publication date: April 4, 2024
    Inventors: Kuo Hua HUANG, Cheng Hsiang HSUEH, I Chiao TSO
  • Publication number: 20240113615
    Abstract: A Totem Pole PFC circuit includes at least one fast-switching leg, a slow-switching leg, and a control unit. Each fast-switching leg includes a fast-switching upper switch and a fast-switching lower switch. The slow-switching leg is coupled in parallel to the at least one fast-switching leg, and the slow-switching leg includes a slow-switching upper switch and a slow-switching lower switch. The control unit receives an AC voltage with a phase angle, and the control unit includes a current detection loop, a voltage detection loop, and a control loop. The control loop generates a second control signal assembly to respectively control the slow-switching upper switch and the slow-switching lower switch. The control loop controls the second control signal assembly to follow the phase angle, and dynamically adjusts a duty cycle of the second control signal assembly to turn on or turn off the slow-switching upper switch and the slow-switching lower switch.
    Type: Application
    Filed: February 22, 2023
    Publication date: April 4, 2024
    Inventors: Chun-Hao HUANG, Chun-Wei LIN, I-Hsiang SHIH, Ching-Nan WU, Jia-Wei YEH
  • Publication number: 20240113429
    Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.
    Type: Application
    Filed: August 16, 2023
    Publication date: April 4, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Sheng-Chin Hsu, Chia-Hung Chen, Chih-Wei Liao, Hau Yuen Tan, Hao-Hsiang Yang, Shih-Keng Huang
  • Publication number: 20240113460
    Abstract: An electrical connector is configured to couple to a butt plug. The electrical connector includes an insulation body, plural signal terminals, plural ground terminals, and at least one conductive plastic. The insulation body has an accommodating recess. The signal terminals are located in the accommodating recess. The ground terminals are located in the accommodating recess, and the ground terminals and the signal terminals are arranged at intervals. The conductive plastic is located on a top surface of the insulation body facing the butt plug. When the butt plug is inserted into the accommodating recess of the insulation body, plural ground terminals of the butt plug are in electrical contact with the conductive plastic.
    Type: Application
    Filed: February 2, 2023
    Publication date: April 4, 2024
    Inventors: Kuo Hua HUANG, Cheng Hsiang HSUEH, I Chiao TSO
  • Publication number: 20240114561
    Abstract: Certain aspects of the present disclosure provide techniques for handling collisions between multiple universal subscriber identity module (MUSIM) gaps and measurement gaps (MGs) or other MUSIM gaps. In an exemplary method, a user equipment (UE) detects a collision between a first multiple universal subscriber identity module (MUSIM) gap occasion and at least one of a second MUSIM gap occasion or a measurement gap (MG) occasion; and processes signals in at least one of the first MUSIM gap occasion, the second MUSIM gap occasion, a third MUSIM gap occasion, or the MG occasion based on relative priorities of the first MUSIM gap occasion, the second MUSIM gap occasion, or the MG occasion.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Carlos CABRERA MERCADER, Arvind Vardarajan SANTHANAM, Ozcan OZTURK, Chu-Hsiang HUANG, Changhwan PARK, Prashant SHARMA
  • Publication number: 20240114540
    Abstract: Aspects described herein relate to receiving, from a network node, an indication of information related to a configuration, including at least one of a modulation and coding scheme (MCS), a physical downlink shared channel (PDSCH) duration, a scrambling sequence, or a reference signal location, used for transmitting downlink signals to one or more co-scheduled UEs, receiving, from the network node, a downlink signal intended for the UE, wherein the signal is interfered by one or more interference signals transmitted to the one or more co-scheduled UEs, and removing, based on the indication, the one or more interference signals from the downlink signal. Other aspects relate to transmitting the information and downlink signals.
    Type: Application
    Filed: August 7, 2023
    Publication date: April 4, 2024
    Inventors: Chu-Hsiang HUANG, Jae Won YOO, Andreas Maximilian SCHENK, Jae HO RYU, Hari SANKAR, Gaurav NIGAM, Changhwan PARK
  • Patent number: 11949016
    Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Chih-Hsuan Chen, Bwo-Ning Chen, Cha-Hon Chou, Hsin-Wen Su, Chih-Hsiang Huang
  • Patent number: 11947254
    Abstract: A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsu-Ting Huang, Shih-Hsiang Lo, Ru-Gun Liu
  • Patent number: 11949015
    Abstract: A method includes following steps. A semiconductor fin is formed extending from a substrate. A gate structure is formed extending across the semiconductor fin. Recesses are etched in the semiconductor fin. Source/drain epitaxial structures are formed in the recesses in the semiconductor fin. Formation of each of the source/drain epitaxial structures comprises performing a first epitaxy growth process to form a bar-shaped epitaxial structure in one of the recesses, and performing a second epitaxy growth process to form a cladding epitaxial layer cladding on the bar-shaped epitaxial structure. The bar-shaped epitaxial structure has a lower phosphorous concentration than the cladding epitaxial layer.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Chi Yang, Chih-Hsiang Huang
  • Patent number: 11947634
    Abstract: An image object classification method and system are disclosed. The method is executed by a processor coupled to a memory. The method includes: providing an image file including at least one image object, performing a process of extracting multiple binary-classified characteristics on the image object to obtain a plurality of first results independent of each other in categories, combining the plurality of first results in a manner of dimensionality reduction based on concatenation, performing a process of characteristics abstraction on the combined first results to obtain a second result, and performing a process of characteristics integration on the plurality of first results and the second result in a manner of dot product of matrices to obtain a classification result.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 2, 2024
    Assignee: Footprintku Inc.
    Inventors: Yan-Jhih Wang, Kuan-Hsiang Tseng, Jun-Qiang Wei, Shih-Feng Huang, Tzung-Pei Hong, Yi-Ting Chen
  • Publication number: 20240107414
    Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Yu-Chieh HUANG, Kuhn-Chang LIN, Jen-Chun CHANG, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yeong Leong CHOO, Chun-Hsiang CHIU, Chihhung HSIEH, Kai-Chun CHENG, Chung Wei LIN
  • Publication number: 20240105659
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over a semiconductor die. A portion of the RDL contacts a die pad of the semiconductor die. A metal layer is formed on a top surface and sidewalls of the RDL and configured to encase the RDL. A non-conductive layer is formed over the metal layer and underlying RDL. An opening in the non-conductive layer is formed exposing a portion of the metal layer formed on the RDL. An under-bump metallization (UBM) is formed in the opening and conductively connected to the die pad by way of the metal layer and RDL.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Inventors: Kuan-Hsiang Mao, Yufu Liu, Wen Hung Huang, Tsung Nan Lo
  • Publication number: 20240105619
    Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
  • Patent number: 11942390
    Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Sheh Huang, Yu-Hsiang Chen, Chii-Ping Chen
  • Patent number: 11938157
    Abstract: Provided is Lactobacillus paracasei TCI727, deposited in the Deutsche Sammlung von Mikroorganismen und Zellkulturen GmbH (DSMZ) with a deposit number of DSM 33756. A method for improving calcium absorption of a subject in need thereof by using the Lactobacillus paracasei TCI727 or metabolites thereof is also provided. The method includes administering to the subject an effective amount of a composition comprising the Lactobacillus paracasei TCI727 or the metabolites thereof.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: March 26, 2024
    Assignee: TCI CO., LTD.
    Inventors: Yung-Hsiang Lin, Chu-Han Huang