Patents by Inventor Hsiang Huang

Hsiang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240073555
    Abstract: The present disclosure discloses an image processing apparatus having lens color-shading correction mechanism. A first and a second calibration circuits perform lens color-shading correction on an input image according to a first and a second calibration parameters to generate a first and a second calibrated images. A first and a second statistic circuits perform statistic on the first and the second calibrated images to generate a first and a second statistic results.
    Type: Application
    Filed: July 20, 2023
    Publication date: February 29, 2024
    Inventors: SHENG-KAI CHEN, HUI-CHUN LIEN, WEN-TSUNG HUANG, SHIH-HSIANG YEN, SZU-PO HUANG
  • Publication number: 20240073531
    Abstract: An automatic target image acquisition and calibration system for application in a defect inspection system is disclosed. During the defect inspection system working normally, the automatic target image acquisition and calibration system is configured to find a recognition structure from an article under inspection, and then determines a relative position and a relative 3D coordinate if the article. Therefore, a robotic arm is controlled to carry a camera to precisely face each of a plurality of inspected surfaces of the article, such that a plurality of article images are acquired by the camera. It is worth explaining that, during the defect inspection of the article, there is no need to modulate an image acquiring height and an image acquiring angle of the camera and an illumination of a light source.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 29, 2024
    Inventors: FENG-TSO SUN, YI-TING YEH, FENG-YU SUN, JYUN-TANG HUANG, RONG-HUA CHANG, YI-HSIANG TIEN, MENG-TSE SHEN
  • Patent number: 11914821
    Abstract: A touch sensitive processing method, comprising: performing capacitance sensing by a touch panel to gather an approximating or touching position of an external conductive object with regard to the touch panel; determining whether the approximating or touching position is within a non-report area, wherein a shape of the non-report area is a circle or an ellipse; when the approximating or touching position is determined outside the non-report area, reporting the approximating or touching position to a host; and when the approximating or touching position is determined inside the non-report area, ignoring the approximating or touching position.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: February 27, 2024
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventors: Chin-Hsiang Chao, Chun-Jung Huang
  • Publication number: 20240064936
    Abstract: A fluid immersion cooling system has a fluid tank containing a hydrocarbon dielectric fluid as a coolant fluid. One or more components of an electronic system is immersed in the coolant fluid. A gas cylinder contains a non-flammable, compressed filling gas. The temperature of the coolant fluid is monitored during operation of the electronic system. The filling gas is released from the gas cylinder and into the fluid tank when the temperature of the coolant fluid rises to a trigger temperature that is set based on the flash point of the coolant fluid. The filling gas covers a surface of the coolant fluid to block oxygen from interacting with vapors of the coolant fluid to prevent combustion.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Inventors: Yueh-Ming LIU, Hsiao-Chung CHEN, Chia-Wei CHEN, Yu-Hsiang HUANG, Chia-Che CHANG, Hua-Kai TONG, Tan-Hsin CHANG, Yu-Chuan CHANG, Ming-Yu CHEN, Yu-Yen HSIUNG, Kun-Chieh LIAO
  • Patent number: 11906730
    Abstract: A lens protection device includes a housing, a first and a second sliding cover. The housing includes an opening and a connecting portion. The first sliding cover includes a first cover plate, a first connecting shaft, and a first and a second magnet. One end of the first connecting shaft connects to the first cover plate and another end pivotally connects to the connecting portion. The first connecting shaft is rotated to move the first cover plate. The first and the second magnet are disposed at a front and a rear end of the first cover plate, respectively. The second sliding cover includes a second cover plate and a second connecting shaft. One end of the second connecting shaft connects to the second cover plate, and another end pivotally connects to the connecting portion. The second connecting shaft is rotated to move the second cover plate.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 20, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Mao-Hsiang Huang, Pen-Uei Lu, Wei-Chih Hsu
  • Patent number: 11908853
    Abstract: An integrated circuit includes a cell layer including a first cell and a second cell, a first metal layer over the cell layer and having a first conductive feature, a second metal layer over the first metal layer and having a second conductive feature, and a first via between the first metal layer and the second metal layer and connecting the first conductive feature to the second conductive feature. The first conductive feature spans over a boundary between the first and second cells, and has a lengthwise direction along a first direction. The second conductive feature spans over the boundary between the first and second cells, and has a lengthwise direction along a second direction that is perpendicular to the first direction.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang, Hiranmay Biswas, Sheng-Hsiung Chen, Aftab Alam Khan
  • Publication number: 20240053315
    Abstract: A gas sampling mechanism protecting an odor sensor and permeable membrane against direct exposure to the gas molecules of an external environment provides a one-way airflow, and includes an inlet chamber, a pump chamber connected to the inlet chamber, and a pump assembly connected to the pump chamber. The pump chamber can compress or evacuate air inside the pump chamber. An inlet valve is moveably arranged between the inlet chamber and the pump, and an outlet valve is movably arranged between the pump chamber and the ambient.
    Type: Application
    Filed: January 5, 2023
    Publication date: February 15, 2024
    Inventor: PO-HSIANG HUANG
  • Publication number: 20240053401
    Abstract: Briefly, embodiments, such as methods, systems and/or circuits for controlling a power signal to be supplied to a processing device. In one aspect, a magnitude of a power supplied to a processing device may be changed based, at least in part on an estimated and/or predicted load.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 15, 2024
    Inventors: Chi-Hsiang Huang, Shidhartha Das, Benoit Labbe
  • Patent number: 11901228
    Abstract: In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cai-Ling Wu, Hsiu-Wen Hsueh, Wei-Ren Wang, Po-Hsiang Huang, Chii-Ping Chen, Jen Hung Wang
  • Publication number: 20240042486
    Abstract: An ultrasonic transducer device includes a first electrode, an insulating layer, an oscillating membrane, a second electrode, and a third electrode. The insulating layer is disposed on the first electrode. The oscillating membrane is disposed over the insulating layer. A cavity is between the oscillating membrane and the insulating layer. The second electrode is disposed on the oscillating membrane. The third electrode is disposed in the cavity and has a plurality of first electrode openings overlapping the second electrode. The second electrode and the third electrode are each located at different sides of the oscillating membrane.
    Type: Application
    Filed: December 6, 2022
    Publication date: February 8, 2024
    Applicant: AUO Corporation
    Inventors: Zhen Wah Chew, Zheng-Han Chen, Pin-Hsiang Chiu, Tai-Hsiang Huang
  • Patent number: 11895847
    Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: February 6, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ting-Hsiang Huang, Yi-Chung Sheng, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Chih-Kai Kang
  • Publication number: 20240030587
    Abstract: An antenna assembly adapted to be assembled to a desktop computer includes a shielding body and an antenna body. The shielding body includes a first wall, two first shielding walls, and two second shielding walls. The first wall is connected to the two first shielding walls and the two second shielding walls and faces an outside of the desktop computer. The antenna body is at the first wall of the shielding body, and one or more portion of the antenna body is connected to the first shielding wall or the second shielding wall. The antenna body is operated at a frequency range of 2400 MHz and 2500 MHz or between 5150 MHz and 7125 MHz.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 25, 2024
    Inventors: Ching-Hsiang Huang, Yu-Ting Kao
  • Publication number: 20240021468
    Abstract: In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.
    Type: Application
    Filed: August 8, 2023
    Publication date: January 18, 2024
    Inventors: Yu-Hsin Chan, Cai-Ling Wu, Chang-Wen Chen, Po-Hsiang Huang, Yu-Yu Chen, Kuan-Wei Huang, Jr-Hung Li, Jay Chiu, Ting-Kui Chang
  • Publication number: 20240021441
    Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.
    Type: Application
    Filed: July 24, 2023
    Publication date: January 18, 2024
    Inventors: Ching-Yi Lin, Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Jyh Chwen Frank Lee, Shuo-Mao Chen
  • Publication number: 20240021560
    Abstract: A semiconductor device includes a first connector, a second connector, and a redistribution structure disposed between the first connector and the second connector. The redistribution structure includes a first connection tree electrically connecting the first connector to the second connector. The first connection tree includes a plurality of first conductive pads disposed in a plurality of respective levels, and a plurality of first via structures each disposed between adjacent ones of the plurality of first conductive pads. Any lateral end of each of the plurality of first conductive pads is spaced from the first connector within a first minimum pitch associated with the second connector.
    Type: Application
    Filed: July 14, 2022
    Publication date: January 18, 2024
    Applicant: Taiwan Semicondutor Manufacturing Company, Ltd.
    Inventors: Ting-Yu Yeh, Han-Hsiang Huang, Chun-Hsien Wen, Chih-Wei Chang
  • Publication number: 20240020457
    Abstract: A cell region of a semiconductor device, the cell region including: components (representing a first circuit) including alpha info conductors and dummy conductors which are substantially collinear correspondingly with reference tracks, regarding the first circuit, the alpha info conductors beipng correspondingly for one or more input and/or output signals, or one or more internal signals, and for a majority of the reference tracks, first ends correspondingly of the alpha info conductors or the dummy conductors being aligned and proximal to a first side of the cell region; a first alpha info conductor being on a first reference track and being an intra-cell conductor which does not extend beyond the first side nor a second side of the cell region; and a portion of a first beta info conductor of a second circuit (represented by components of an external cell region) being on the first reference track.
    Type: Application
    Filed: July 31, 2023
    Publication date: January 18, 2024
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Sheng-Hsiung CHEN, Po-Hsiang HUANG
  • Patent number: 11876945
    Abstract: A method for acquiring shadow-free images of a document for scanning or other purposes is applied in a device. The method includes training a shadow prediction model based on sample documents of a sample library and inputting a background color and a shadow mask of each of the sample documents extracted by the shadow prediction model into a predetermined shadow removing network for training, to obtain a shadow removing model. The method further includes obtaining a background color and a shadow mask of the document through the shadow prediction model and removing the shadows of the document based on the shadow removing model. The device utilizing the method is also disclosed.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: January 16, 2024
    Assignee: Mobile Drive Netherlands B.V.
    Inventors: Yun-Hsuan Lin, Yung-Yu Chuang, Nai-Sheng Syu, Tzu-Kuei Huang, Ting-Hao Chung, Yu-Ching Wang, Chun-Hsiang Huang
  • Publication number: 20240013425
    Abstract: An object location method to obtain location information of an object based on positioning light comprises: emitting a first positioning light, to scan a preset region where the object is located to obtain a characteristic value of each of multiple standard regions in the preset region, wherein the preset region comprises multiple standard regions; determining a basic region where the object is located according to the characteristic value of each standard region, wherein each of the standard region comprises multiple basic regions; and emitting a second positioning light to the basic regions where the object is located and to obtain coordinates of the object. An electronic device and a non-transitory storage medium are also provided.
    Type: Application
    Filed: November 29, 2022
    Publication date: January 11, 2024
    Inventors: CHUN-HSIANG HUANG, PO-HSUN HUANG
  • Publication number: 20240014120
    Abstract: A package structure includes a circuit substrate, a semiconductor package, first bump structures and second bump structures. The semiconductor package is disposed on the circuit substrate, wherein the semiconductor package includes a center region and side regions surrounding the center region. The first bump structures are disposed on the center region of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate. The second bump structures are disposed on the side regions of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate, wherein the first bump structures and the second bump structures have different heights and different shapes.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Lin, Han-Hsiang Huang, Chien-Sheng Chen, Shu-Shen Yeh, Shin-Puu Jeng
  • Patent number: 11861282
    Abstract: A method of manufacturing an IC structure includes forming a first plurality of fins extending in a first direction on a substrate, a second plurality of fins extending adjacent to the first plurality of fins, a third plurality of fins extending adjacent to the second plurality of fins, and a fourth plurality of fins extending adjacent to the third plurality of fins. Each fin of the first and fourth pluralities of fins includes one of an n-type or p-type fin, each fin of the second and third pluralities of fins includes the other of the n-type or p-type fin, each of the first and third pluralities of fins includes a first total number of fins, and each of the second and fourth pluralities of fins includes a second total number of fins fewer than the first total number of fins.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsiang Huang, Fong-Yuan Chang, Clement Hsingjen Wann, Chih-Hsin Ko, Sheng-Hsiung Chen, Li-Chun Tien, Chia-Ming Hsu