Abstract: A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and a pad voltage terminal. The second body terminal is coupled to a first node. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The second transistor is in a second well different from the first well, and is separated from the first well in a first direction.

Abstract: An antenna module includes: a first insulation medium substrate, including a first section provided with a first groove and a second section, where an integrated circuit is disposed in the first groove; a flexible substrate including a conductive structure, where the flexible substrate is stacked on the first insulation medium substrate, and a part that is of the flexible substrate and that is located between the first section and the second section is bendable; and an antenna structure, including a first metal structure that is disposed on the first section and that is connected to the conductive structure and the integrated circuit, and a second metal structure that is disposed on the second section and that is connected to the conductive structure. This avoids a warping problem caused by different thermal expansion coefficients of a plastic packaging material and a substrate, and reduces a risk of product failure.

Abstract: A power supply circuit in a wireless communications system includes an envelope tracking modulator coupled to a first power amplifier circuit and a second power amplifier circuit, so that the power supply circuit supplies power to the first power amplifier circuit and the second power amplifier circuit. When a transmit signal output by a processor is within a first bandwidth range, the power supply circuit supplies power to the first power amplifier circuit, and the first power amplifier circuit amplifies power of the transmit signal. When the transmit signal output by the processor meets a second bandwidth range, the power supply circuit supplies power to the second power amplifier circuit, and the second power amplifier circuit amplifies the transmit signal.

Abstract: A radio frequency signal generation method and related apparatus are provided, for reducing interference of counter 3rd order intermodulation products (CIM3) to a guard band without increasing costs and power consumption of a device that generates radio frequency signals. The terminal device includes an application processor, a baseband processor, a local oscillator, and an up-converter. The application processor is configured to trigger the baseband processor to send a resource block (RB) signal. The baseband processor is configured to: determine an offset ?f of a center frequency of the RB signal relative to a zero frequency, and control the local oscillator to adjust a center frequency flo of a local oscillation signal generated by the local oscillator to flo+?f.

Abstract: A method of transmit power control in a mobile telecommunications device is provided. One of a plurality of signal paths providing different output power and different gains is assigned in a first gain adjustment and a first power measurement in a current time slot. The same one of the signal paths is assigned in at least a second gain adjustment and a second power measurement in the same current time slot.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A switching power amplifier includes: a first transistor controlled by a first digital signal to selectively output a first output signal; a second transistor controlled by a second digital signal to selectively output a second output signal; and a control circuit arranged to generate the second digital signal according to the first digital signal and a third digital signal; wherein the first output signal and the second output signal are outputted on a common connected node of the first transistor and the second transistor.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A transmit power measurement apparatus includes a transmit power detection path, a compensation circuit and a tracking circuit. The compensation circuit includes a programmable filter device and a compensation controller. The programmable filter device generates a filter output. The compensation controller sets the programmable filter device at least based on a frequency response of the transmit power detection path. The tracking circuit generates a transmit power tracking result at least based on the filter output.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A method operative on a wireless transceiver device for performing beamforming calibration includes: measuring at least one joint signal response of at least one circuit loopback between a transmitter of the wireless transceiver device and a receiver of the wireless transceiver device to determine the measurement result; and calibrating joint signal path mismatch according to the measurement result for s multiple antenna beamforming system operating on the wireless transceiver device.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A modulation circuit includes a phase locked loop (PLL) circuit, a scalar circuit and a sigma-delta modulator. The PLL circuit is for generating an output oscillating signal in response to a reference signal, a first control signal and a second control signal. The scalar circuit is for generating the first control signal in response to modulating data to control frequency deviation of the output oscillating signal, wherein the first control signal is in a digital form. The sigma-delta modulator is for generating the second control signal according to the modulating data to modulate a divider value of a frequency divider of the PLL circuit.

Abstract: A data converting device includes: a data sampling circuit arranged to up-sample a digital signal to generate an up-sampling signal according to a clock signal; a voltage level generating circuit arranged to generate an adjustable voltage; and a signal converting circuit arranged to generate a converting signal according to the adjustable voltage and the up-sampling signal.

Abstract: A transmitter device with I/Q mismatch compensation and a method thereof are provided. The transmitter device includes a transmitter circuit, a loop-back circuit and a baseband circuit. The transmitter circuit is configured to convert a baseband signal into an RF signal based on a specific gain configuration of a plurality of gain configurations. The loop-back circuit is configured to retrieve the RF signal from the transmitter circuit. The baseband circuit is configured to compensate the baseband signal by specific transmitter I/Q mismatch corresponding to the specific gain configuration, wherein a plurality of transmitter IQ mismatches are determined for the plurality of gain configurations by the retrieved RF signal, and the specific transmitter I/Q mismatch among the plurality of transmitter IQ mismatches is determined by the retrieved RF signal, which is converted in response to the specific gain configuration, from the loop-back circuit.

Abstract: A method operative on a wireless transceiver device for performing beamforming calibration includes: measuring at least one joint signal response of at least one circuit loopback between a transmitter of the wireless transceiver device and a receiver of the wireless transceiver device to determine the measurement result; and calibrating joint signal path mismatch according to the measurement result for s multiple antenna beamforming system operating on the wireless transceiver device.

Abstract: A signal transmitting device includes: a signal processing circuit arranged to process an input signal to generate a processed input signal according to a compensating signal; a signal converting circuit arranged to convert the processed input signal to generate an output signal according to an oscillating signal; and an arithmetic circuit arranged to generate the compensating signal according to the power of a predetermined component in the output signal, wherein the signal processing circuit uses the compensating signal to update the input signal, and the signal converting circuit converts the updated input signal to reduce the power of the predetermined component in the output signal.

Abstract: A modulation circuit includes a phase locked loop (PLL) circuit, a scalar circuit and a sigma-delta modulator. The PLL circuit is for generating an output oscillating signal in response to a reference signal, a first control signal and a second control signal. The scalar circuit is for generating the first control signal in response to modulating data to control frequency deviation of the output oscillating signal, wherein the first control signal is in a digital form. The sigma-delta modulator is for generating the second control signal according to the modulating data to modulate a divider value of a frequency divider of the PLL circuit.

Abstract: A method of transmit power control in a mobile telecommunications device is provided. One of a plurality of signal paths providing different output power and different gains is assigned in a first gain adjustment and a first power measurement in a current time slot. The same one of the signal paths is assigned in at least a second gain adjustment and a second power measurement in the same current time slot.