Abstract: A digital-controlled oscillator (DCO) is utilized in an all-digital phase-locked loop for eliminating frequency discontinuities. The DCO includes a tank module and a negative gm cell. The tank module comprises a plurality of cells, at least a portion of the cells comprising a first tracking set and a second tracking set for respectively handling an odd bit or an even bit. The odd bit and the even bit are related to an integer signal, a fractional signal or a combination thereof, the fractional signal is indicated by a primary voltage inputted to the DCO. With the DCO, frequency discontinuities and undesired spurs are eliminated.

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract: Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error o a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with only digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By modulating certain parameters within the ADPLL by following an all-pass frequency response, a loop gain of the ADPLL may be precisely modulated, and an available bandwidth of the ADPLL is also significantly broadened.

Abstract: A MASH modulator. The MASH modulator receives a fractional input value, generates an integer output value, and comprises three cascaded first order sigma delta modulators (SDMS) each comprising an accumulator, a plurality of first multipliers, a second multiplier, a first adder, and a second adder. Each of the first multipliers is coupled to a corresponding accumulator. The first adder receives the fractional input value. The second multiplier is coupled between the first adder and the cascaded first order sigma delta modulators. The second adder is coupled to the cascaded first order sigma delta modulators to generate the integer output value.

Abstract: Phase frequency detectors with limited output pulse width and related methods are provided. On exemplary phase frequency detector includes a first edge detector, a second edge detector, and a pulse reshaping controller. The first edge detector is for detecting first-type edges of a first signal to generate a first detection signal. The second edge detector is for detecting the first-type edges of a second signal to generate a second detection signal. The pulse reshaping controller is for receiving the first detection signal and the second detection signal, and for generating a first control signal to the first edge detector and generating a second control signal to the second edge detector. In addition, the pulse reshaping controller further generates a first output signal and a second output signal, wherein a pulse width of the first output signal is limited by the pulse reshaping controller.

Abstract: Phase frequency detectors with limited output pulse width and related methods are disclosed. The proposed phase frequency detector generates a first output signal and a second output signal corresponding to phase difference or frequency difference between a first signal and a second signal. When the phase difference between the first and second signals is greater than a predetermined delay, the pulse width of the first output signal is limited, so that the proposed phase frequency detector has a limited equivalent output pulse width.

Abstract: A stereo decoding system comprises an oscillator, a bandpass filter, a PLL unit and a stereo decoder. The oscillator generates a first signal with a center frequency. The bandpass filter receives a stereo multiplexed signal and the first signal to filter out a pilot signal. The PLL unit receives the pilot signal to generate a PLL output signal. The stereo decoder receives the stereo multiplexed signal and the PLL output signal to separate a left channel signal and a right channel signal from the stereo multiplexed signal.

Abstract: A method of frequency search for a digitally controlled oscillator (DCO) with multiple sub-bands. The method comprises providing multiple workable pre-control codes, each control code comprising a most significant bit (MSB), corresponding to each frequency of the DCO for selection, selecting one of the workable pre-control codes according to the MSBs thereof, and providing the selected control code to the DCO.

Abstract: A FM receiver comprises an IF filter, a demodulator and a decoder. The IF filter generates an RSSI and a FM modulated signal in response to a FM signal. The demodulator comprises a duty-to-voltage amplifier for amplifying a peak of a MPX signal. The duty-to-voltage amplifier comprises a current source, a switch and a current splitter. The current source generates a current. The switch controls a flow of the first current in response to a PWM signal. The current splitter splits the flow of the current into a sub-flow in response to the RSSI. The peak of the MPX signal is proportional to the sub-flow. The decoder receives the MPX signal to generate an audio signal to play sound.

Abstract: A stereo decoder and a method therefor are provided. The stereo decoder receives a MPX signal from an FM demodulator, and comprises a first auto-calibration circuit, a band-pass filter, a second auto-calibration circuit, a slicer and a PLL circuit. The first auto-calibration circuit generates a first control signal. The band-pass filter generates the pilot signal by filtering the MPX signal with a center frequency set by the first control signal. The second auto-calibration circuit generates a second control signal. The slicer converts the pilot signal into a square wave signal. The PLL circuit comprises a voltage controlled oscillator for generating an oscillation frequency in response to the second control signal. The PLL circuit receives the square wave signal to generate the reference signal around the predetermined frequency in response to the oscillation frequency.

Abstract: Methods and apparatuses for demodulating an incoming signal are disclosed. A proposed demodulator includes: a first pulse generator for generating a first control signal according to an incoming signal; a second pulse generator coupled to the first pulse generator for generating a second control signal according to the incoming signal and the first control signal; and an output buffer coupled to the first pulse generator and the second pulse generator for generating an output signal under the control of the first and second control signals, wherein the magnitude of the output signal is clamped when the frequency of the incoming signal is lower than a predetermined threshold.

Abstract: Phase frequency detectors with limited output pulse width and related methods are disclosed. The proposed phase frequency detector generates a first output signal and a second output signal corresponding to phase difference or frequency difference between a first signal and a second signal. When the phase difference between the first and second signals is greater than a predetermined delay, the pulse width of the first output signal is limited, so that the proposed phase frequency detector has a limited equivalent output pulse width.

Abstract: A voltage controlled delay line having a plurality of delay cells is used to delay a first reference clock by a predetermined delay time to generate an in-phase first delay clock and to delay a second reference clock by the predetermined delay time to generate an in-phase second delay clock. Each delay cell has a first input port, a second input port, a first output port, and a second output port. The first output port of one delay cell and the second input port of another one delay cell having the same phase are electrically connected or the second output port of one delay cell and the first input port of another one delay cell having the same phase are electrically connected so that the first and second input port of each delay cell are not connected to the first and second output port of an adjacent delay cell.

Abstract: A voltage controlled delay line having a plurality of delay cells is used to delay a first reference clock by a predetermined delay time to generate an in-phase first delay clock and to delay a second reference clock by the predetermined delay time to generate an in-phase second delay clock. Each delay cell has a first input port, a second input port, a first output port, and a second output port. The first output port of one delay cell and the second input port of another one delay cell having the same phase are electrically connected or the second output port of one delay cell and the first input port of another one delay cell having the same phase are electrically connected so that the first and second input port of each delay cell are not connected to the first and second output port of an adjacent delay cell.

Abstract: The present invention provides a delta-sigma-modulator for converting an external analog signal to a digital out-put signal. The delta-sigma modulator comprises a first filter circuit, a second filter circuit, a one-bit quantization, a multi-bit quantization, a digital-to-analog converter, and a digital filter. The first filter circuit outputs a first analog signal according to the external analog signal and an one-bit output signal. The second filter circuit outputs a third analog signal according to the first analog signal and a second analog signal. The one-bit quantization converts the third analog signal into the one-bit output signal. The multi-bit quantization converts the third analog signal into a multi-bit output signal. The digital-to-analog converter comprises a plurality of capacitors, and determines the number of capacitors to be charged according to the multi-bit output signal, then selects the capacitors to be charged in a predetermined turn and charges the capacitors.

Abstract: The present invention provides a delta-sigma modulator for converting an external analog signal to a digital output signal. The delta-sigma modulator comprises a first filter circuit, a second filter circuit, a one-bit quantization, a multi-bit quantization, a digital-to-analog converter, and a digital filter. The first filter circuit outputs a first analog signal according to the external analog signal and an one-bit output signal. The second filter circuit outputs a third analog signal according to the first analog signal and a second analog signal. The one-bit quantization converts the third analog signal into the one-bit output signal. The multi-bit quantization converts the third analog signal into a multi-bit output signal. The digital-to-analog converter comprises a plurality of capacitors, and determines the number of capacitors to be charged according to the multi-bit output signal, then selects the capacitors to be charged in a predetermined turn and charges the capacitors.