Abstract: An oscillating circuit including a digital sigma-delta modulator and a controlled oscillator is disclosed. The digital sigma-delta modulator receives a fractional bit signal to generate a control signal. The controlled oscillator includes a varactor dynamically coupled to receive the control signal.

Abstract: An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.

Abstract: A mixed-mode PLL is disclosed. The mixed-mode PLL comprises a digital sigma-delta modulator, a low pass filter, and a digital controlled oscillator. The digital sigma-delta modulator receives a fractional bit signal. The low pass filter is coupled to the digital sigma-delta modulator. The low pass filter receives an output signal of the digital sigma-delta modulator and converts the output signal to an analog control signal. The digital controlled oscillator comprises a varactor dynamically coupled to the low pass filter and receiving the analog control signal.

Abstract: A calibration circuit for calibrating an output level of a demodulator includes a test signal generator, an RSSI module and a calibration module. The test signal generator generates a test signal, and the RSSI module detects the test signal to generate a control signal, wherein the control signal controls the demodulator to process the test signal to generate a determined output signal. The calibration module then calibrates the RSSI module according to the output signal in order to calibrate the output level of the demodulator. When the control signal is utilized to selectively enable or disable a soft-mute function of the demodulator, the calibration module can be utilized to calibrate or determine the soft-mute function of the demodulator.

Abstract: An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract: Phase frequency detectors with limited output pulse width and related methods are provided. On exemplary phase frequency detector includes a first edge detector, a second edge detector, and a pulse reshaping controller. The first edge detector is for detecting first-type edges of a first signal to generate a first detection signal. The second edge detector is for detecting the first-type edges of a second signal to generate a second detection signal. The pulse reshaping controller is for receiving the first detection signal and the second detection signal, and for generating a first control signal to the first edge detector and generating a second control signal to the second edge detector. In addition, the pulse reshaping controller further generates a first output signal and a second output signal, wherein a pulse width of the first output signal is limited by the pulse reshaping controller.

Abstract: A stereo decoding system comprises an oscillator, a bandpass filter, a PLL unit and a stereo decoder. The oscillator generates a first signal with a center frequency. The bandpass filter receives a stereo multiplexed signal and the first signal to filter out a pilot signal. The PLL unit receives the pilot signal to generate a PLL output signal. The stereo decoder receives the stereo multiplexed signal and the PLL output signal to separate a left channel signal and a right channel signal from the stereo multiplexed signal.

Abstract: A mixed-mode PLL is disclosed. The mixed-mode PLL comprises a digital sigma-delta modulator, a low pass filter, and a digital controlled oscillator. The digital sigma-delta modulator receives a fractional bit signal. The low pass filter is coupled to the digital sigma-delta modulator. The low pass filter receives an output signal of the digital sigma-delta modulator and converts the output signal to an analog control signal. The digital controlled oscillator comprises a varactor dynamically coupled to the low pass filter and receiving the analog control signal.

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract: An amplitude modulation circuit in a polar transmitter and a method for calibrating amplitude offset in the polar transmitter are provided. The amplitude modulation circuit includes a digital-to-analog converter (DAC), a low pass filter (LPF), a gm stage, and a calibration module. The DAC is coupled to an amplitude modulation signal input. The LPF is coupled to the DAC, and the gm stage is coupled to the LPF. The calibration module has an input coupled to the gm stage, and an output coupled to a node on a path between the DAC and the gm stage. The method includes: generating an amplitude offset calibration signal according to an amplitude modulation signal generated from the gm stage; and transmitting the amplitude offset calibration signal via the output of the calibration module to a node on a path between the DAC and the gm stage so as to calibrate the amplitude offset.

Abstract: A digital-controlled oscillator (DCO) is utilized in an all-digital phase-locked loop for eliminating frequency discontinuities. The DCO includes a tank module and a negative gm cell. The tank module comprises a plurality of cells, at least a portion of the cells comprising a first tracking set and a second tracking set for respectively handling an odd bit or an even bit. The odd bit and the even bit are related to an integer signal, a fractional signal or a combination thereof, the fractional signal is indicated by a primary voltage inputted to the DCO. With the DCO, frequency discontinuities and undesired spurs are eliminated.

Abstract: A transmitter for transmitting and calibrating a phase signal and an amplitude signal. The transmitter comprises a phase modulation path, an amplitude modulation path, and a control unit. The phase modulation path transmits the phase signal. The amplitude modulation path transmits the amplitude signal. The control unit delays the signal on at least one of the phase modulation path and the amplitude modulation.

Abstract: A FM receiver comprises an IF filter, a demodulator and a decoder. The IF filter generates an RSSI and a FM modulated signal in response to a FM signal. The demodulator comprises a duty-to-voltage amplifier for amplifying a peak of a MPX signal. The duty-to-voltage amplifier comprises a current source, a switch and a current splitter. The current source generates a current. The switch controls a flow of the first current in response to a PWM signal. The current splitter splits the flow of the current into a sub-flow in response to the RSSI. The peak of the MPX signal is proportional to the sub-flow. The decoder receives the MPX signal to generate an audio signal to play sound.

Abstract: A calibration circuit for calibrating an output level of a demodulator includes a test signal generator, an RSSI module and a calibration module. The test signal generator generates a test signal, and the RSSI module detects the test signal to generate a control signal, wherein the control signal controls the demodulator to process the test signal to generate a determined output signal. The calibration module then calibrates the RSSI module according to the output signal in order to calibrate the output level of the demodulator. When the control signal is utilized to selectively enable or disable a soft-mute function of the demodulator, the calibration module can be utilized to calibrate or determine the soft-mute function of the demodulator.

Abstract: An oscillator is disclosed. The oscillator comprises a cycle controller and a re-cycle delay line module. The cycle controller generates a cycle control signal. The re-cycle delay line module produces a periodic signal. The re-cycling delay line module performs a re-cycling operation. The number of re-cycling in the re-cycling operation is determined based on the cycle control signal.

Abstract: A FM receiver comprises an IF filter, a demodulator and a decoder. The IF filter generates an RSSI and a FM modulated signal in response to a FM signal. The demodulator comprises a duty-to-voltage amplifier for amplifying a peak of a MPX signal. The duty-to-voltage amplifier comprises a current source, a switch and a current splitter. The current source generates a current. The switch controls a flow of the first current in response to a PWM signal. The current splitter splits the flow of the current into a sub-flow in response to the RSSI. The peak of the MPX signal is proportional to the sub-flow. The decoder receives the MPX signal to generate an audio signal to play sound.

Abstract: Time to digital converters (TDCs) with high resolution are disclosed. The TDC includes a first time to digital converting module, a selection and time amplifying module, a second time to digital converting module and a decoder, and is applied in estimating a time difference between a first signal and a second signal. As the delay time of the delay units of the time to digital converting modules is the unit of the time difference measurement, the first and second time to digital converting modules are responsible for the integral portion and the fractional portion of the estimated time difference, respectively. Moreover, by introducing the normalization process, the linearity of the converting characteristic of the TDC can be improved; by adding an error detection circuit to the TDC, the possible metastable problem can be prevented.

Abstract: A MASH modulator. The MASH modulator receives a fractional input value, generates an integer output value, and comprises three cascaded first order sigma delta modulators (SDMs) each comprising an accumulator, a plurality of first multipliers, a second multiplier, a first adder, and a second adder. Each of the first multipliers is coupled to a corresponding accumulator. The first adder receives the fractional input value. The second multiplier is coupled between the first adder and the cascaded first order sigma delta modulators. The second adder is coupled to the cascaded first order sigma delta modulators to generate the integer output value.

Abstract: An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.