Patents by Inventor Hsiang Lin
Hsiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961939Abstract: A method of manufacturing a light-emitting device, including: providing a substrate structure including a top surface; forming a precursor layer on the top surface; removing a portion of the precursor layer and a portion of the substrate from the top surface to form a base portion and a plurality of protrusions regularly arranged on the base portion; forming a buffer layer on the base portion and the plurality protrusions; and forming a III-V compound cap layer on the buffer layer; wherein one of the plurality of protrusions comprises a first portion and a second portion formed on the first portion; wherein the first portion is integrated with the base portion and has a first material which is the same as that of the base portion; and wherein the buffer layer contacts side surfaces of the plurality of protrusions and a surface of the base portion.Type: GrantFiled: June 23, 2022Date of Patent: April 16, 2024Assignee: EPISTAR CORPORATIONInventors: Peng Ren Chen, Yu-Shan Chiu, Wen-Hsiang Lin, Shih-Wei Wang, Chen Ou
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Patent number: 11961951Abstract: A light emitting diode device includes a substrate, a conductive via, first and second conductive pads, a driving chip, a flat layer, a redistribution layer, a light emitting diode, and an encapsulating layer. The substrate has a first surface and a second surface opposite thereto. The conductive via penetrates from the first surface to the second surface. The first and second conductive pads are respectively disposed on the first and second surface and in contact with the conductive via. The driving chip is disposed on the first surface. The flat layer is disposed over the first surface and covers the driving chip and the first conductive pad. The redistribution layer is disposed on the flat layer and electrically connects to the driving chip. The light emitting diode is flip-chip bonded to the redistribution layer. The encapsulating layer covers the redistribution layer and the light emitting diode.Type: GrantFiled: July 22, 2021Date of Patent: April 16, 2024Assignee: Lextar Electronics CorporationInventors: Chih-Hao Lin, Jian-Chin Liang, Shih-Lun Lai, Jo-Hsiang Chen
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Patent number: 11963385Abstract: The disclosure provides a local stretch packaging structure, including a substrate, a flexible electronic element, a plurality of light-emitting display elements, and a packaging layer. The flexible electronic element is disposed on the substrate. These light-emitting display elements are disposed on the flexible electronic element. The packaging layer includes a packaging area and a non-packaging area. The packaging area covers the upper surface and sidewalls of these light-emitting display elements. The non-packaging area is directly covered the flexible electronic element that is not disposed with these light-emitting display elements.Type: GrantFiled: October 25, 2021Date of Patent: April 16, 2024Assignees: Interface Technology (ChengDu) Co., Ltd., Interface Optoelectronics (ShenZhen) Co., Ltd., General Interface Solution LimitedInventors: Wen-You Lai, Ping-Hsiang Kao, Po-Lun Chen, Chun-Ta Chen, Po-Ching Lin, Ya-Chu Hsu
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Patent number: 11961770Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: GrantFiled: November 4, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
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Patent number: 11959512Abstract: A frame pool is disclosed including a frame assembly and a pool liner, the frame assembly including horizontal frame members and a vertical frame member coupled together via a T-shaped joint. The T-shaped joint may be constructed of plastic to facilitate attachment and detachment to the adjacent frame members and to resist galling and corrosion. The T-shaped joint may also be relatively small to improve the appearance and water containment of the frame pool.Type: GrantFiled: May 16, 2023Date of Patent: April 16, 2024Assignee: Intex Marketing Ltd.Inventors: Hua Hsiang Lin, Yaw Yuan Hsu
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Publication number: 20240120162Abstract: A key structure is provided. The key structure includes an elastic element and a keycap disposed on the elastic element. The elastic element includes a movable portion, a fixed portion and a connection portion. The fixed portion surrounds the movable portion. The connection portion connects the fixed portion with the movable portion. The keycap includes a first connection portion. The first connection portion is connected to the fixed portion or the movable portion.Type: ApplicationFiled: September 28, 2023Publication date: April 11, 2024Inventors: Ko-Hsiang LIN, Chun-Lin CHEN
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Publication number: 20240121373Abstract: Disclosed are an image display method and a 3d display system. The method is adapted to the 3d display system including a 3d display device and includes the following steps. A first image and a second image are obtained by splitting an input image according to a 3d image format. Whether the input image is a 3D format image complying with the 3D image format is determined through a stereo matching processing performed on the first image and the second image. An image interweaving process is enabled to be performed on the input image to generate an interweaving image in response to determining that the input image is the 3D format image complying with the 3D image format, and the interweaving image is displayed via the 3D display device.Type: ApplicationFiled: May 10, 2023Publication date: April 11, 2024Applicant: Acer IncorporatedInventors: Kai-Hsiang Lin, Hung-Chun Chou, Wen-Cheng Hsu, Shih-Hao Lin, Chih-Haw Tan
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Publication number: 20240118618Abstract: A method of manufacturing a semiconductor device includes forming a first layer having an organic material over a substrate. A second layer is formed over the first layer, wherein the second layer includes a silicon-containing polymer having pendant acid groups or pendant photoacid generator groups. The forming a second layer includes: forming a layer of a composition including a silicon-based polymer and a material containing an acid group or photoacid generator group over the first layer, floating the material containing an acid group or photoacid generator group over the silicon-based polymer, and reacting the material containing an acid group or photoacid generator group with the silicon-based polymer to form an upper second layer including a silicon-based polymer having pendant acid groups or pendant photoacid generator groups overlying a lower second layer comprising the silicon-based polymer. A photosensitive layer is formed over the second layer, and the photosensitive layer is patterned.Type: ApplicationFiled: April 12, 2023Publication date: April 11, 2024Inventors: Chun-Chih HO, Ching-Yu Chang, Chin-Hsiang Lin
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Publication number: 20240120304Abstract: The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.Type: ApplicationFiled: November 24, 2022Publication date: April 11, 2024Applicant: Innolux CorporationInventors: Tzu-Sheng Wu, Haw-Kuen Liu, Chung-Jyh Lin, Cheng-Chi Wang, Wen-Hsiang Liao, Te-Hsun Lin
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Patent number: 11955460Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.Type: GrantFiled: October 5, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
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Patent number: 11955338Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.Type: GrantFiled: January 30, 2023Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
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Patent number: 11953740Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.Type: GrantFiled: May 14, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Publication number: 20240113552Abstract: Power supplies and methods of use thereof are provided, where a power supply includes an input configured to receive input AC power an output configured to provide output AC power to a load, at least one power converter coupled to the input and configured to convert the input AC power into the output AC power, a controller coupled the at least one power converter. The controller is configured to adjust at least one parameter of the output AC power provided by the at least one power converter, detect, in response to adjusting the at least one parameter of the output AC power, at least one of an adjusted input AC power or an adjusted output AC power, and determine that a fault has occurred based on the at least one of the adjusted input AC power or the adjusted output AC power.Type: ApplicationFiled: December 13, 2023Publication date: April 4, 2024Inventors: Kenneth A. Colby, JR., Wei-Hsiang Lin, Venkatraman Chennakesavan, Eyob Demissie, Luka Petrovic, Himamshu V Prasad, Yu Zhang
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Publication number: 20240111377Abstract: A touch detection circuitry includes an analog-to-digital converter (ADC), a controller, and a packet generator. The ADC is arranged to convert touch signals of a touch panel from analog form into digital form. The controller is electrically connected to the ADC, and is configured to calculate at least one coordinate point and at least one touch size respectively corresponding to at least one touch event on the touch panel based on the touch signals. The packet generator is electrically connected to the controller, and is configured to encapsulate the at least one coordinate point and the at least one touch size into a touch data packet.Type: ApplicationFiled: June 7, 2023Publication date: April 4, 2024Inventors: Yu Nian OU, Chun Kai CHUANG, Yu-Hsiang LIN, Chun-Lung TSAI
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Publication number: 20240113615Abstract: A Totem Pole PFC circuit includes at least one fast-switching leg, a slow-switching leg, and a control unit. Each fast-switching leg includes a fast-switching upper switch and a fast-switching lower switch. The slow-switching leg is coupled in parallel to the at least one fast-switching leg, and the slow-switching leg includes a slow-switching upper switch and a slow-switching lower switch. The control unit receives an AC voltage with a phase angle, and the control unit includes a current detection loop, a voltage detection loop, and a control loop. The control loop generates a second control signal assembly to respectively control the slow-switching upper switch and the slow-switching lower switch. The control loop controls the second control signal assembly to follow the phase angle, and dynamically adjusts a duty cycle of the second control signal assembly to turn on or turn off the slow-switching upper switch and the slow-switching lower switch.Type: ApplicationFiled: February 22, 2023Publication date: April 4, 2024Inventors: Chun-Hao HUANG, Chun-Wei LIN, I-Hsiang SHIH, Ching-Nan WU, Jia-Wei YEH
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Method for reducing UPS component stresses during transition from inverter to green/bypass operation
Patent number: 11947402Abstract: UPS systems, methods, and computer-readable mediums utilizing electromechanical bypass relays to switch from an on-line mode of operation to a green/bypass mode of operation include control logic to adaptively adjust the timing of when an inverter of a UPS turns off to prevent backfeeding a utility. After the UPS is instructed to transition from the on-line mode to the green mode, a monitoring period begins. During the monitoring period, a parameter related to the output current of the inverter is monitored and compared to a predetermined threshold. If the parameter exceeds the predetermined threshold before a fixed period time has elapsed, the inverter is turned off early. If the inverter current does not exceed the predetermined value within the fixed period of time, the inverter is turned off.Type: GrantFiled: March 7, 2023Date of Patent: April 2, 2024Assignee: SCHNEIDER ELECTRIC IT CORPORATIONInventors: Wei-Hsiang Lin, Adam Daniel Sanner -
Patent number: 11948497Abstract: A display device includes a plurality of sub-pixels. The sub-pixels include a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first light emitting element and a first control circuit. The first control circuit is configured to provide a first driving current to the first light emitting element. The second sub-pixel includes a second light emitting element and a second control circuit. The second control circuit is configured to provide a second driving current to the second light emitting element. The first control circuit and the second control circuit are configured to differently control pulse amplitude of the first driving current and pulse amplitude of the second driving current, such that both of the first light emitting element and the second light emitting element emit at a target wavelength or a color point range (e.g. +/?1.5˜2 nm).Type: GrantFiled: August 30, 2021Date of Patent: April 2, 2024Assignee: Lextar Electronics CorporationInventors: Chih-Hao Lin, Chien-Nan Yeh, Jo-Hsiang Chen, Shih-Lun Lai
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Patent number: 11949056Abstract: The light emitting diode packaging structure includes a flexible substrate, a first adhesive layer, micro light emitting elements, a conductive pad, a redistribution layer, and an electrode pad. The first adhesive layer is disposed on the flexible substrate. The micro light emitting elements are disposed on the first adhesive layer and have a first surface facing to the first adhesive layer and an opposing second surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting element. The redistribution layer covers the micro light emitting elements and the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer. A thickness of the flexible substrate is less than 100 um.Type: GrantFiled: April 20, 2023Date of Patent: April 2, 2024Assignee: Lextar Electronics CorporationInventors: Chih-Hao Lin, Jo-Hsiang Chen, Shih-Lun Lai, Min-Che Tsai, Jian-Chin Liang
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Patent number: 11949016Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.Type: GrantFiled: May 13, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hao Lin, Chih-Chuan Yang, Chih-Hsuan Chen, Bwo-Ning Chen, Cha-Hon Chou, Hsin-Wen Su, Chih-Hsiang Huang
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Patent number: 11947694Abstract: A method, a computer program product, and a system for implementing a dynamic virtual database honeypot. The method includes relaying a query request received from a database client to a database and receiving, from the database, a response relating to the query request. The method also includes determining the query request is an attack on the database based on session information relating to the database and the database client, generating a honey token based on information contained within the response, generating an alternate response formatted in a same format as the response and containing artificial information that masks the information contained within the response. The method further includes inserting the honey token into the alternate response and transmitting the alternate response to the database client.Type: GrantFiled: June 29, 2021Date of Patent: April 2, 2024Assignee: International Business Machines CorporationInventors: Galia Diamant, Richard Ory Jerrell, Chun-Shuo Lin, Wei-Hsiang Hsiung, Cheng-Ta Lee, Wei-Jie Liau