Patents by Inventor Hsiang-Ming Huang

Hsiang-Ming Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7906333
    Abstract: A surface modification method of polysaccharide, the modified polysaccharide, and a method of culturing and recovery cells using the same are provided. The surface modification method of polysaccharide comprises (a) immersing a polysaccharide material in an acid, (b) immersing the polysaccharide material in an acidic solution containing a protein, and (c) immersing the polysaccharide material in an alkaline solution containing bivalent metal ions.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: March 15, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Jen Liao, Yung-chih Wu, Chen-Chi Tsai, Hsiang-Ming Huang, Yuan-Hua Hsu, Shu-Fang Chiang
  • Publication number: 20100007001
    Abstract: Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.
    Type: Application
    Filed: July 10, 2009
    Publication date: January 14, 2010
    Inventors: David Wei Wang, An-Hong Liu, Hao-Yin Tsai, Hsiang-Ming Huang, Yi-Chang Lee, Shu-Ching Ho
  • Patent number: 7642639
    Abstract: An IC package to enhance the bondibility of embedded bumps, primarily includes a substrate having a plurality of bump-accommodating holes, a bumped chip, an encapsulant, and a plurality of external terminals. The substrate further has a plurality of inner pads at one ends of the bump-accommodating holes respectively. The inner pads may be meshed or a soldering layer is disposed thereon for improving bump connection. The chip is attached to the substrate with the bumps aligned and embedded in the corresponding bump-accommodating holes. The encapsulant is at least formed on a lower surface of the substrate to encapsulate the meshes or the soldering layer. By the suspended meshes or/and the soldering layer, the bumps can be easily bonded at lower temperatures to simplify the manufacturing process with shorter electrical conductive paths and thinner package profiles without wire sweeping.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: January 5, 2010
    Assignees: ChipMos Technologies Inc., ChipMos Technologies (Bermuda) Ltd.
    Inventors: Hsiang-Ming Huang, An-Hong Liu, Yeong-Jyh Lin, Yi-Chang Lee
  • Publication number: 20090283905
    Abstract: A conductive structure of a chip is provided. The conductive structure comprises a ground layer, a dielectric layer, a redistribution layer, an under bump metal and a solder bump. The ground layer electrically connects to the ground pad of the chip, while the dielectric layer overlays the ground layer. Thus, the conductive layer can result in impedance matching, and the packaged chip is adapted to transmit a high frequency signal.
    Type: Application
    Filed: October 31, 2008
    Publication date: November 19, 2009
    Inventors: Hsiang-Ming HUANG, An-Hong Liu, Yi-Chang Lee, Hao-Yin Tsai, Shu-Ching Ho
  • Publication number: 20090236741
    Abstract: A conductive structure of a chip and a method for manufacturing the conductive structure are provided. An under bump metal (UBM) is formed on the redistribution layer (RDL) by performing an electroless plating process. Subsequently, the solder bump is formed on the under bump metal for electrical connection. Thus, the photomask can be economized and the cost of manufacturing can be reduced.
    Type: Application
    Filed: October 31, 2008
    Publication date: September 24, 2009
    Inventors: Hsiang-Ming HUANG, An-Hong Liu, Yi-Chang Lee, Hao-Yin Tsai, Shu-Ching Ho
  • Patent number: 7554197
    Abstract: A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: June 30, 2009
    Assignees: ChipMOS Technologies (Bermuda) Ltd, ChipMOS Technologies Inc.
    Inventors: Hsiang-Ming Huang, An-Hong Liu, Yeong-Jyh Lin, Yi-Chang Lee, Wu-Chang Tu, Chun-Hung Lin, Shih Feng Chiu
  • Patent number: 7477065
    Abstract: A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: January 13, 2009
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Yi-Chang Lee, An-Hong Liu, Yeong-Her Wang, Yeong-Ching Chao, Hsiang-Ming Huang
  • Publication number: 20080124828
    Abstract: MEMS processes for fabrication of a MEMS alloy probe are revealed. Multiple layers of the MEMS alloy probe are formed on the substrate in sequences as a first surface layer, a first conductive layer, a core layer, a second conductive layer, and a second surface layer where the width of the first conductive layer is smaller than the one of first surface layer so that all the exposed edges of the first surface layer are not covered by the first conductive layer. The second surface layer is extended from the sidewalls of the core layer to the exposed edges of the first surface layer to encapsulate the core layer, the first conductive layer, and the second conductive layer. The MEMS alloy probe fabricated by the MEMS processes can eliminate the issue of oxidation.
    Type: Application
    Filed: November 20, 2006
    Publication date: May 29, 2008
    Inventors: Hsiang-Ming Huang, An-Hong Liu, Shu-Ching Ho, Yi-Chang Lee, Yeong-Jyh Lin
  • Patent number: 7372286
    Abstract: A modular probe card comprises a printed circuit board, an interposer, and a probe head where the printed circuit board has a plurality of first contact pads, the probe head has a plurality of second contact pads. The interposer is disposed between the printed circuit board and the probe head where the interposer includes a substrate and a plurality of pogo pins. The substrate has a first surface, a second surface, and a plurality of through holes penetrating from the first surface to the second surface. The pogo pins are secured in the through holes of the substrate.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: May 13, 2008
    Assignees: ChipMOS Technologies (Bermuda) Ltd., ChipMOS Technologies Inc.
    Inventors: Yi-Chang Lee, An-Hong Liu, Hsiang-Ming Huang, Yao-Jung Lee, Yeong-Her Wang
  • Patent number: 7368809
    Abstract: A pillar grid array package (PGA) includes a substrate, a chip disposed on top of the substrate, and a plurality of stud bumps disposed on bottom of the substrate. The stud bumps are formed in an array and each has a flattened top to electrically connect to a printed circuit board, PCB, by an anisotropic conductive paste to achieve a thin package and to avoid substrate warpage problems of a ball grid array (BGA) during high-temperature reflow processes.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: May 6, 2008
    Assignees: ChipMOS Technologies (Bermuda) Ltd., ChipMOS Technologies Inc.
    Inventors: Hsiang-Ming Huang, Yeong-Ching Chao, Yi-Chang Lee, An-Hong Liu
  • Patent number: 7316065
    Abstract: A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: January 8, 2008
    Assignees: ChipMOS Technologies (Bermuda), ChipMOS Technologies Inc.
    Inventors: Yi-Chang Lee, An-Hong Liu, Yeong-Her Wang, Yeong-Ching Chao, Hsiang-Ming Huang
  • Publication number: 20070262439
    Abstract: An IC package to enhance the bondibility of embedded bumps, primarily includes a substrate having a plurality of bump-accommodating holes, a bumped chip, an encapsulant, and a plurality of external terminals. The substrate further has a plurality of inner pads at one ends of the bump-accommodating holes respectively. The inner pads may be meshed or a soldering layer is disposed thereon for improving bump connection. The chip is attached to the substrate with the bumps aligned and embedded in the corresponding bump-accommodating holes. The encapsulant is at least formed on a lower surface of the substrate to encapsulate the meshes or the soldering layer. By the suspended meshes or/and the soldering layer, the bumps can be easily bonded at lower temperatures to simplify the manufacturing process with shorter electrical conductive paths and thinner package profiles without wire sweeping.
    Type: Application
    Filed: October 20, 2006
    Publication date: November 15, 2007
    Inventors: Hsiang-Ming Huang, An-Hong Liu, Yeong-Jyh Lin, Yi-Chang Lee
  • Publication number: 20070235871
    Abstract: A high frequency IC package mainly includes a substrate, a bumped chip, and a plurality of conductive fillers where the substrate has a plurality of bump holes penetrating from the top surface to the bottom surface. The active surface of the chip is attached to the top surface of the substrate in a manner that the bumps are inserted into the bump holes respectively. The conductive fillers are formed in the bump holes to electrically connect the bumps to the circuit layer of the substrate. The high frequency IC package has a shorter electrical path and a thinner package thickness.
    Type: Application
    Filed: April 10, 2006
    Publication date: October 11, 2007
    Inventors: Hsiang-Ming Huang, An-Hong Liu, Yeong-Jyh Lin, Yi-Chang Lee, Wu-Chang Tu, Chun-Hung Lin, Shih Chiu
  • Publication number: 20070222465
    Abstract: A vertical probe head primarily comprise a substrate, a trace layer, and a plurality of vertical probes where the substrate has a first surface, a second surface, and a plurality of device holes penetrating through the first surface and the second surface. The trace layer is formed on the first surface. Each vertical probe has a bonding end and a probing end where the bonding ends are inserted into the device holes of the substrate and are electrically connected to the trace layer and the probing ends are protruded away from the second surface of the substrate. Resins are filled into the device holes to firmly fix the vertical probes so that the vertical probes will not easily be bent nor damaged.
    Type: Application
    Filed: November 15, 2006
    Publication date: September 27, 2007
    Inventors: Hsiang-Ming Huang, An-Hong Liu, Yi-Chang Lee, Yao-Jung Lee
  • Publication number: 20070152689
    Abstract: A modular probe card comprises a printed circuit board, an interposer, and a probe head where the printed circuit board has a plurality of first contact pads, the probe head has a plurality of second contact pads. The interposer is disposed between the printed circuit board and the probe head where the interposer includes a substrate and a plurality of pogo pins. The substrate has a first surface, a second surface, and a plurality of through holes penetrating from the first surface to the second surface. The pogo pins are secured in the through holes of the substrate.
    Type: Application
    Filed: January 3, 2006
    Publication date: July 5, 2007
    Inventors: Yi-Chang Lee, An-Hong Liu, Hsiang-Ming Huang, Yao-Jung Lee, Yeong-Her Wang
  • Publication number: 20070148768
    Abstract: A surface modification method of polysaccharide, the modified polysaccharide, and a method of culturing and recovery cells using the same are provided. The surface modification method of polysaccharide comprises (a) immersing a polysaccharide material in an acid, (b) immersing the polysaccharide material in an acidic solution containing a protein, and (c) immersing the polysaccharide material in an alkaline solution containing bivalent metal ions.
    Type: Application
    Filed: March 21, 2006
    Publication date: June 28, 2007
    Inventors: Chun-Jen Liao, Yung-chih Wu, Chen-Chi Tsai, Hsiang-Ming Huang, Yuan-Hua Hsu, Shu-Fang Chiang
  • Publication number: 20070085554
    Abstract: A replaceable modular probe head is composed of a plurality of in-parallel probing modules. Each probing module has a plurality of in-series probing regions. In the present embodiment, each probing module has mechanical connection parts on its both ends to attach to a printed circuit board (PCB) to be a multi-DUT probe card. Therefore, the probing module can be replaced individually when probes are damaged or worn without replacing the whole probe head to reduce the fabrication cost of a multi-DUT probe head.
    Type: Application
    Filed: October 14, 2005
    Publication date: April 19, 2007
    Inventors: Hsiang-Ming Huang, An-Hong Liu, Yi-Chang Lee, Yao-Jung Lee, Yeong-Her Wang
  • Publication number: 20070080452
    Abstract: A bump structure mainly includes a metal core, a buffer encapsulant, and a metal cap where the metal core is a stud bump formed by wire bonding. The buffer encapsulant encapsulates the metal core. A metal cap is formed on the top surface of the buffer encapsulant and is electrically connected to the metal core. Therefore, the bump structure possesses excellent resistance of thermal stress to reduce or even eliminate metal fatigue in the bump without causing electrical shorts in the package.
    Type: Application
    Filed: September 1, 2006
    Publication date: April 12, 2007
    Inventors: Chen-Ya- Chi, Chun-Ying Lin, An-Hong Liu, Yi-Chang Lee, Hsiang-Ming Huang
  • Publication number: 20070069749
    Abstract: A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.
    Type: Application
    Filed: November 29, 2006
    Publication date: March 29, 2007
    Inventors: Yi-Chang Lee, An-Hong Liu, Yeong-Her Wang, Yeong-Ching Chao, Hsiang-Ming Huang
  • Publication number: 20070069750
    Abstract: A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.
    Type: Application
    Filed: November 29, 2006
    Publication date: March 29, 2007
    Inventors: Yi-Chang Lee, An-Hong Liu, Yeong-Her Wang, Yeong-Ching Chao, Hsiang-Ming Huang