Abstract: A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.

Abstract: A pillar grid array package (PGA) includes a substrate, a chip disposed on top of the substrate, and a plurality of stud bumps disposed on bottom of the substrate. The stud bumps are formed in an array and each has a flattened top to electrically connect to a printed circuit board, PCB, by an anisotropic conductive paste to achieve a thin package and to avoid substrate warpage problems of a ball grid array (BGA) during high-temperature reflow processes.

Abstract: An image sensor module package is disclosed. A plurality of connecting pads are formed on a first surface of a glass substrate having and located outside a light entering area. A via-redistribution layer is formed on an opposing second surface of the glass substrate. A plurality of vias penetrate the glass substrate to electrically connect the via-redistribution layer with the connecting pads. A bumped image sensor chip is flip-chip attached to the second surface of the glass substrate so that a sensing area of the image sensor chip is corresponding to a light entering area of the glass substrate without blocking the via-redistribution layer. The connecting pads may connect to a plurality of solder balls or a FPC. In one embodiment, a plurality of passive components can be placed on the via-redistribution layer to enhance the electrical performance and the functions of the image sensor module package.

Abstract: The invention discloses a chip-under-tape package structure including a flexible substrate, a chip, a plurality of connecting members, a plurality of stud bumps, and a potting adhesive. The flexible substrate includes a plurality of inner pads and a plurality of outer pads. The chip is attached to a lower surface of the flexible substrate and has an active surface thereon providing a plurality of bonding pads which each corresponds to one of the inner pads. Each of the connecting members functions electrically connecting one of the bonding pads with the inner pad corresponding to said one bonding pad. Each of the stud bumps is attached to one of the outer pads. The potting adhesive is coated to seal the connecting members. Accordingly, the invention is capable of preventing the outer pads from being contaminated by the potting adhesive and suitable for low-cost package of high frequency memory chip.