Patents by Inventor Hsiang-Pang Li

Hsiang-Pang Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210240443
    Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 5, 2021
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Hung-Sheng Chang, Han-Wen Hu, Hsiang-Pang Li, Tzu-Hsien Yang, I-Ching Tseng, Hsiang-Yun Cheng, Chia-Lin Yang
  • Patent number: 11050440
    Abstract: An encoding method includes: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 29, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Huai Shih, Yu-Ming Huang, Hsiang-Pang Li, Hsi-Chia Chang
  • Publication number: 20210119645
    Abstract: The present invention discloses an encoder, a decoder, an encoding method and a decoding method based on Low-Density Parity-Check (LDPC) code. The encoding method comprises: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.
    Type: Application
    Filed: October 21, 2019
    Publication date: April 22, 2021
    Inventors: Chih-Huai SHIH, Yu-Ming HUANG, Hsiang-Pang LI, Hsi-Chia CHANG
  • Publication number: 20210081140
    Abstract: The present disclosure provides a memory system, a method of operating memory, and a non-transitory computer readable storage medium. The memory system includes a memory chip and a controller. The controller is coupled with the memory chip, which the controller is configured to: receive a first data corresponding to a first version from a file system in order to store the first data corresponding to the first version in a first page of the flash memory chip; and program the first data corresponding to a second version in the first page in response to the first data of the second version, which the second version is newer than the first version.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Ping-Hsien LIN, Wei-Chen WANG, Hsiang-Pang LI, Shu-Hsien LIAO, Che-Wei TSAO, Yuan-Hao CHANG, Tei-Wei KUO
  • Publication number: 20200312405
    Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.
    Type: Application
    Filed: February 21, 2020
    Publication date: October 1, 2020
    Applicant: MACRONIX International Co., Ltd.
    Inventors: SHU-YIN HO, Hsiang-Pang Li, Yao-Wen Kang, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 10671296
    Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 2, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hung-Sheng Chang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 10447436
    Abstract: A method for generating a polar code includes the steps of: establishing a plurality of polarization matrices that receive a plurality of first input bits via a plurality of first input channels and provide a plurality of first output bits on a plurality of first output channels; selecting at least one to-be-enhanced input channel from the first input channels of the polarization matrices; providing a re-polarization matrix that receives a plurality of second input bits via a plurality of second input channels and provides a plurality of second output bits on a plurality of second output channels, wherein a part of the second output bits is used as the first output bit(s) on the at least one to-be-enhanced input channel; and providing a polar code that comprises the first output bits and a remaining part of the second output bits.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 15, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Ming Huang, Chih-Huai Shih, Hsiang-Pang Li, Hsi-Chia Chang
  • Publication number: 20190245653
    Abstract: A method for generating a polar code includes the steps of: establishing a plurality of polarization matrices that receive a plurality of first input bits via a plurality of first input channels and provide a plurality of first output bits on a plurality of first output channels; selecting at least one to-be-enhanced input channel from the first input channels of the polarization matrices; providing a re-polarization matrix that receives a plurality of second input bits via a plurality of second input channels and provides a plurality of second output bits on a plurality of second output channels, wherein a part of the second output bits is used as the first output bit(s) on the at least one to-be-enhanced input channel; and providing a polar code that comprises the first output bits and a remaining part of the second output bits.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 8, 2019
    Inventors: Yu-Ming HUANG, Chih-Huai SHIH, Hsiang-Pang LI, Hsi-Chia CHANG
  • Publication number: 20190073136
    Abstract: A memory controlling method, a memory controlling circuit and a memory system are provided. A memory includes a plurality of memory chips. The memory controlling method includes the following steps: The memory chips are grouped into at least two partner groups by a grouping unit. A quantity of the memory chips in each of the partner groups is at least two. At least one of the memory chips in each of the partner groups is required to serve a reading request or a writing request by a processing unit.
    Type: Application
    Filed: September 6, 2017
    Publication date: March 7, 2019
    Inventors: Hung-Sheng Chang, Hsiang-Pang Li, Tse-Yuan Wang, Che-Wei Tsao, Yuan-Hao Chang, Tei-Wei Kuo
  • Publication number: 20190050156
    Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.
    Type: Application
    Filed: August 9, 2017
    Publication date: February 14, 2019
    Inventors: Hung-Sheng Chang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
  • Publication number: 20190034118
    Abstract: A data management method for a memory device includes: counting a system time; when at least a part of a block of the memory device is accessed or refreshed or programmed at first time, assigning a block number of the block to point to a maximum remaining retention time; when a first downgrade trigger time reaches, assigning the block number to point from the maximum remaining retention time to a medium remaining retention time; when a second downgrade trigger time reaches, assigning the block number to point from the medium remaining retention time to a minimum remaining retention time; and once the block number points to the minimum remaining retention time, refreshing the block and assigning the block number to point to the maximum remaining retention time.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 31, 2019
    Inventors: Hung-Sheng Chang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 10128982
    Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N?K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q?K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q?K frozen bits are allocated to the N?K frozen bit-channels and the q additional frozen bit-channels.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 13, 2018
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Ming Huang, Hsiang-Pang Li, Hsie-Chia Chang
  • Patent number: 10120605
    Abstract: A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: November 6, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hung-Sheng Chang, Yu-Ming Chang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 10049764
    Abstract: A control method for a memory device is provided. The control method includes the following steps. Convert multiple input bits on multiple bit-channels into a code word through a polar code transformation. Select a boundary bit-channel among the bit-channels according to a first ranking list for the bit-channels. Identify a target memory cell among the memory cells according to the boundary bit-channel and a generator matrix of the polar code transformation. Decrease a raw bit error rate of the target memory cell.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: August 14, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Ming Huang, Hsiang-Pang Li, Kun-Cheng Hsu, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 10007446
    Abstract: A method for writing data into a persistent storage device includes grouping a plurality of data entries stored in a temporary storage device to form a data unit, such that the data unit has a size equal to an integer multiple of a size of an access unit of the persistent storage device. The method further includes writing the data unit into the persistent storage device.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: June 26, 2018
    Assignee: Macronix International Co., Ltd.
    Inventors: Wei-Chieh Huang, Li-Chun Huang, Yu-Ming Chang, Hung-Sheng Chang, Hsiang-Pang Li, Ting-Yu Liu, Chien-Hsin Liu, Nai-Ping Kuo
  • Publication number: 20180166148
    Abstract: A control method for a memory device is provided. The control method includes the following steps. Convert multiple input bits on multiple bit-channels into a code word through a polar code transformation. Select a boundary bit-channel among the bit-channels according to a first ranking list for the bit-channels. Identify a target memory cell among the memory cells according to the boundary bit-channel and a generator matrix of the polar code transformation. Decrease a raw bit error rate of the target memory cell.
    Type: Application
    Filed: June 6, 2017
    Publication date: June 14, 2018
    Inventors: Yu-Ming Huang, Hsiang-Pang Li, Kun-Cheng Hsu, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 9817588
    Abstract: A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: November 14, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Ming Chang, Wei-Chieh Huang, Li-Chun Huang, Hung-Sheng Chang, Hsiang-Pang Li, Ting-Yu Liu, Chien-Hsin Liu, Nai-Ping Kuo
  • Patent number: 9760488
    Abstract: A cache system is provided. The cache system includes a first cache and a second cache. The first cache is configured for storing a first status of a plurality of data. The second cache is configured for storing a table. The table includes the plurality of data arranged from a highest level to a lowest level. The cache system is configured to update the first status of the plurality of data in the first cache. The cache system is further configured to update the table in the second cache according to the first status of the plurality of data.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: September 12, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hung-Sheng Chang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 9754637
    Abstract: An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: September 5, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Ming Chang, Hsiang-Pang Li, Hsin-Yu Chang, Chien-Chung Ho, Yuan-Hao Chang
  • Patent number: 9740602
    Abstract: An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: August 22, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Ming Chang, Yung-Chun Li, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo