Patents by Inventor Hsiang-Pang Li
Hsiang-Pang Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11704246Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.Type: GrantFiled: December 1, 2021Date of Patent: July 18, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Bo-Rong Lin, Ming-Liang Wei, Hsiang-Pang Li, Nai-Jia Dong, Hsiang-Yun Cheng, Chia-Lin Yang
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Patent number: 11594277Abstract: A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.Type: GrantFiled: July 22, 2022Date of Patent: February 28, 2023Assignee: MACRONIX International Co., Ltd.Inventors: Shu-Yin Ho, Hsiang-Pang Li, Yao-Wen Kang, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo
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Publication number: 20230033998Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.Type: ApplicationFiled: December 1, 2021Publication date: February 2, 2023Inventors: Bo-Rong LIN, Ming-Liang WEI, Hsiang-Pang LI, Nai-Jia DONG, Hsiang-Yun CHENG, Chia-Lin YANG
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Patent number: 11526328Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.Type: GrantFiled: February 4, 2020Date of Patent: December 13, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hung-Sheng Chang, Han-Wen Hu, Hsiang-Pang Li, Tzu-Hsien Yang, I-Ching Tseng, Hsiang-Yun Cheng, Chia-Lin Yang
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Publication number: 20220359003Abstract: A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.Type: ApplicationFiled: July 22, 2022Publication date: November 10, 2022Applicant: MACRONIX International Co., Ltd.Inventors: Shu-Yin Ho, Hsiang-Pang Li, Yao-Wen Kang, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo
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Patent number: 11443797Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.Type: GrantFiled: February 21, 2020Date of Patent: September 13, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shu-Yin Ho, Hsiang-Pang Li, Yao-Wen Kang, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo
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Patent number: 11194515Abstract: The present disclosure provides a memory system, a method of operating memory, and a non-transitory computer readable storage medium. The memory system includes a memory chip and a controller. The controller is coupled with the memory chip, which the controller is configured to: receive a first data corresponding to a first version from a file system in order to store the first data corresponding to the first version in a first page of the flash memory chip; and program the first data corresponding to a second version in the first page in response to the first data of the second version, which the second version is newer than the first version.Type: GrantFiled: September 16, 2019Date of Patent: December 7, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ping-Hsien Lin, Wei-Chen Wang, Hsiang-Pang Li, Shu-Hsien Liao, Che-Wei Tsao, Yuan-Hao Chang, Tei-Wei Kuo
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Publication number: 20210240443Abstract: A computation method and a computation apparatus exploiting weight sparsity, adapted for a processor to perform multiply-and-accumulate operations on a memory including multiple input and output lines crossing each other. In the method, weights are mapped to the cells of each operation unit (OU) in the memory. The rows of the cells of each OU are compressed by removing at least one row of the cells each mapped with a weight of 0, and an index including values each indicating a distance between every two rows of the cells including at least one cell mapped with a non-zero weight for each OU is encoded. Inputs are inputted to the input lines corresponding to the rows of each OU excluding the rows of the cells with the weight of 0 according to the index and outputs are sensed from the output lines corresponding to the OU to compute a computation result.Type: ApplicationFiled: February 4, 2020Publication date: August 5, 2021Applicant: MACRONIX International Co., Ltd.Inventors: Hung-Sheng Chang, Han-Wen Hu, Hsiang-Pang Li, Tzu-Hsien Yang, I-Ching Tseng, Hsiang-Yun Cheng, Chia-Lin Yang
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Patent number: 11050440Abstract: An encoding method includes: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.Type: GrantFiled: October 21, 2019Date of Patent: June 29, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Huai Shih, Yu-Ming Huang, Hsiang-Pang Li, Hsi-Chia Chang
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Publication number: 20210119645Abstract: The present invention discloses an encoder, a decoder, an encoding method and a decoding method based on Low-Density Parity-Check (LDPC) code. The encoding method comprises: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.Type: ApplicationFiled: October 21, 2019Publication date: April 22, 2021Inventors: Chih-Huai SHIH, Yu-Ming HUANG, Hsiang-Pang LI, Hsi-Chia CHANG
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Publication number: 20210081140Abstract: The present disclosure provides a memory system, a method of operating memory, and a non-transitory computer readable storage medium. The memory system includes a memory chip and a controller. The controller is coupled with the memory chip, which the controller is configured to: receive a first data corresponding to a first version from a file system in order to store the first data corresponding to the first version in a first page of the flash memory chip; and program the first data corresponding to a second version in the first page in response to the first data of the second version, which the second version is newer than the first version.Type: ApplicationFiled: September 16, 2019Publication date: March 18, 2021Inventors: Ping-Hsien LIN, Wei-Chen WANG, Hsiang-Pang LI, Shu-Hsien LIAO, Che-Wei TSAO, Yuan-Hao CHANG, Tei-Wei KUO
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Publication number: 20200312405Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.Type: ApplicationFiled: February 21, 2020Publication date: October 1, 2020Applicant: MACRONIX International Co., Ltd.Inventors: SHU-YIN HO, Hsiang-Pang Li, Yao-Wen Kang, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo
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Patent number: 10671296Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.Type: GrantFiled: August 9, 2017Date of Patent: June 2, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hung-Sheng Chang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
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Patent number: 10447436Abstract: A method for generating a polar code includes the steps of: establishing a plurality of polarization matrices that receive a plurality of first input bits via a plurality of first input channels and provide a plurality of first output bits on a plurality of first output channels; selecting at least one to-be-enhanced input channel from the first input channels of the polarization matrices; providing a re-polarization matrix that receives a plurality of second input bits via a plurality of second input channels and provides a plurality of second output bits on a plurality of second output channels, wherein a part of the second output bits is used as the first output bit(s) on the at least one to-be-enhanced input channel; and providing a polar code that comprises the first output bits and a remaining part of the second output bits.Type: GrantFiled: February 7, 2018Date of Patent: October 15, 2019Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Ming Huang, Chih-Huai Shih, Hsiang-Pang Li, Hsi-Chia Chang
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Publication number: 20190245653Abstract: A method for generating a polar code includes the steps of: establishing a plurality of polarization matrices that receive a plurality of first input bits via a plurality of first input channels and provide a plurality of first output bits on a plurality of first output channels; selecting at least one to-be-enhanced input channel from the first input channels of the polarization matrices; providing a re-polarization matrix that receives a plurality of second input bits via a plurality of second input channels and provides a plurality of second output bits on a plurality of second output channels, wherein a part of the second output bits is used as the first output bit(s) on the at least one to-be-enhanced input channel; and providing a polar code that comprises the first output bits and a remaining part of the second output bits.Type: ApplicationFiled: February 7, 2018Publication date: August 8, 2019Inventors: Yu-Ming HUANG, Chih-Huai SHIH, Hsiang-Pang LI, Hsi-Chia CHANG
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Publication number: 20190073136Abstract: A memory controlling method, a memory controlling circuit and a memory system are provided. A memory includes a plurality of memory chips. The memory controlling method includes the following steps: The memory chips are grouped into at least two partner groups by a grouping unit. A quantity of the memory chips in each of the partner groups is at least two. At least one of the memory chips in each of the partner groups is required to serve a reading request or a writing request by a processing unit.Type: ApplicationFiled: September 6, 2017Publication date: March 7, 2019Inventors: Hung-Sheng Chang, Hsiang-Pang Li, Tse-Yuan Wang, Che-Wei Tsao, Yuan-Hao Chang, Tei-Wei Kuo
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Publication number: 20190050156Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.Type: ApplicationFiled: August 9, 2017Publication date: February 14, 2019Inventors: Hung-Sheng Chang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
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Publication number: 20190034118Abstract: A data management method for a memory device includes: counting a system time; when at least a part of a block of the memory device is accessed or refreshed or programmed at first time, assigning a block number of the block to point to a maximum remaining retention time; when a first downgrade trigger time reaches, assigning the block number to point from the maximum remaining retention time to a medium remaining retention time; when a second downgrade trigger time reaches, assigning the block number to point from the medium remaining retention time to a minimum remaining retention time; and once the block number points to the minimum remaining retention time, refreshing the block and assigning the block number to point to the maximum remaining retention time.Type: ApplicationFiled: July 28, 2017Publication date: January 31, 2019Inventors: Hung-Sheng Chang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo
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Patent number: 10128982Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N?K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q?K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q?K frozen bits are allocated to the N?K frozen bit-channels and the q additional frozen bit-channels.Type: GrantFiled: October 6, 2016Date of Patent: November 13, 2018Assignee: Macronix International Co., Ltd.Inventors: Yu-Ming Huang, Hsiang-Pang Li, Hsie-Chia Chang
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Patent number: 10120605Abstract: A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.Type: GrantFiled: April 8, 2016Date of Patent: November 6, 2018Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Hung-Sheng Chang, Yu-Ming Chang, Hsiang-Pang Li, Yuan-Hao Chang, Tei-Wei Kuo