Abstract: A noise elimination device for a Class-D audio amplifier includes a residual signal detector and a multiplexer, wherein the multiplexer is electrically connected with a sigma-delta modulator (SDM) and a pulse width modulator (PWM) of the Class-D audio amplifier and the residual signal detector. The residual signal detector is configured to detect whether an input signal of the Class-D audio amplifier is residual. The multiplexer is configured to output zero data into the pulse width modulator when the residual signal detector detects that the input signal of the Class-D audio amplifier is residual.

Abstract: A buffer circuit is provided to output an output signal at an output node. The buffer circuit includes first and second inverters and first and second switches. The first inverter inverts an input signal. The second inverter is coupled between the first inverter and the output node. The first switch is coupled between a first voltage source terminal and the output node. The second switch is coupled between the output node and a second voltage source terminal. First and second voltages are respectively provided to the first and second voltage source terminals. In response to the input signal switching to a first level from a second level, the first switch is turned on to pre-charge the output node. In response to the input signal transiting to the second level from the first level, the second switch is turned on to pre-discharge the output node.

Abstract: A method is provided for a travelling vehicle to detect lane lines. A front camera module captures frames of front image of the vehicle, a rear camera module captures frames of rear image of the vehicle, and a speed sensor module senses speed trajectory of the vehicle. In the method, the frames of front image, the frames of rear image and the sensed speed trajectory are used to obtain pairs of matched front and rear images, and to determine reliability of a lane line feature detected in a current front image or a current rear image based on the pairs of matched front and rear images, and the lane line feature detected from the current front image or the current rear image is outputted upon determining that the currently detected lane line feature is reliable.

Abstract: A memory operation method, comprising: when a first super block of a memory device is a open block (or in programming state), obtaining a first read count of one of a plurality of first memory blocks in the first super block, wherein the first read count is a number of times that data of one of the first memory blocks is read out; determining whether the first read count is larger than a first threshold; and when the first read count is larger than the first threshold, moving a part of the data in the first super block to a safe area in the memory device, wherein the part of the data comprises data in the first memory block.

Abstract: A server includes a casing, a motherboard, a riser cable holder, a riser cable and an expansion card. The motherboard is located in the casing. The riser cable holder includes a main body, a first holder and a second holder. The main body is fixed in the casing, the first holder and the second holder are respectively connected to different positions of the main body, and the first holder and the second holder are in asymmetric arrangement relative to the main body. The riser cable is mounted on the main body and electrically connected to the motherboard. The first holder and the second holder are detachably engaged with the riser cable. The expansion card is inserted into the riser cable.

Abstract: A structured membrane fabrication method begins with a membrane wafer on a substrate and at least one thin-film on the membrane wafer such that portions of the membrane wafer are exposed. The exposed portions of the membrane wafer and each thin-film are covered with an acetone-inert protectant. Portions of the protectant are etched through to the membrane wafer while each thin-film remains fully covered by the protectant. A handle is coupled to the protectant with a wax that dissolves in acetone. Portions of the substrate are then removed to define and expose a contiguous region of the membrane wafer adjacent to each thin-film and the portions of the protectant so-etched. The wax is exposed to acetone so that it dissolves. The contiguous region of the membrane wafer is then etched through at the portions of the protectant so-etched. The protectant is then removed.

Abstract: An electrophoresis display with high aperture ratio includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of thin film transistors (TFT), a plurality of gate lines, and plurality of data lines. Each of the gate line is connected to the gates of the TFTs and each of the data lines is connected to the sources or the drains of the TFTs. The area of a semiconductor part of the TFT is at least partially overlapped with the area of one of the gate lines or the area of one of the date lines along a projection direction.

Abstract: A method includes forming a photoresist layer over a wafer; aligning a first photomask with a first area of the wafer; performing a first exposure process to a first portion of the photoresist layer within the first area of the wafer; aligning a second photomask with a second area of the wafer, wherein aligning the first photomask and aligning the second photomask are performed using an alignment mark within a stitching zone of the wafer, the stitching zone being an overlapping region of the first area and the second area; performing a second exposure process to a second portion of the photoresist layer within the second area of the wafer; and performing a development process to remove the first and second portions of the photoresist layer.

Abstract: A color electrophoresis display with micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The electrophoresis display further includes a color filter layer arranged on bottom of the chamber. The colloidal solution contains charged black particles and/or charged white particles.

Abstract: An electrophoresis display with color filter structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The electrophoresis display further includes a color filter layer between the control substrate and the electrophoresis layer. The first face is the viewing face of the electrophoresis display.

Abstract: An electrophoresis display with tapered micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The sectional width of the partition wall decreases with a layer number of a polymer stacks forming the partition wall increases.

Abstract: An electrophoresis display includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The viewing face of the electrophoresis display is on the first face of the control substrate. The aperture ratio of the control substrate in the electrophoresis display, viewed from the first face of the control substrate and toward a display area of the electrophoresis display, is not less than 70%.

Abstract: An electrophoresis display with high aperture ratio includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of thin film transistors (TFT), a plurality of gate lines, and plurality of data lines. Each of the gate line is connected to the gates of the TFTs and each of the data lines is connected to the sources or the drains of the TFTs. The sum of the data line width and the gate line width is not larger than 10 ?m. The aperture ratio of the electrophoresis display, viewed from the first face of the control substrate and toward a display area of the electrophoresis display, is not less than 80%.

Abstract: An electrophoresis display with storage capacitor having transparent electrode includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer, and an opposite substrate. The driving circuit layer includes a plurality of storage capacitors. At least the storage capacitors corresponding to the viewing area of the electrophoresis display have a transparent first electrode, a transparent second electrode and an insulating layer between the transparent first electrode and the transparent second electrode.

Abstract: An electrophoresis display double-side control circuit substrate includes a first control substrate having a first face and a second face, a first driving circuit layer and a first control electrode layer sequentially arranged on the second face, a second control substrate having a third face and a fourth face, a second driving circuit layer and a second control electrode layer sequentially arranged on the third face. The electrophoresis display includes a micro partition structure arranged between the first control substrate and the second control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution.

Abstract: An electrophoresis display with embedded touch sensing includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, an electrophoresis layer with electrophoresis material, and a touch with display driver (TDDI) electrically connected to data lines and common voltage lines. When the electrophoresis display performs touch sensing operation, the TDDI electrically connected plurality ones of the data lines into single a touch transmitting electrode or a single touch receiving electrode, and the TDDI electrically connected plurality ones of the common voltage lines into a single touch receiving electrode or a single touch transmitting electrode. The viewing face of the electrophoresis display is on the first face of the electrophoresis display.

Abstract: An electrophoresis display with transparent control electrode includes a transparent control substrate having a first face and a second face, a driving circuit layer, a control electrode layer having a plurality of transparent control electrodes, an electrophoresis layer, and an opposite substrate. The charges of the transparent control electrodes attract the charged color particles with opposite polarity to the charges of the transparent control electrodes toward a face of the electrophoresis layer near the control electrodes, thus forming image for viewer.

Abstract: An electrophoresis display with micro tenon includes a control substrate having a first face and a second face, a driving circuit layer and a control electrode layer sequentially arranged on the second face, an opposite substrate having a third face opposite to the second face and a fourth face, a micro partition structure formed between the second face and the third face. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The electrophoresis display further includes a plurality of micro tenons. Each of the micro tenons is corresponding to a face of the micro partition structure and embedded into one of the chambers.

Abstract: An electrophoresis display with gapped micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. Two adjacent partition walls have a gap therebetween and used as yielding space when the electrophoresis display is bent. The area of the gap is not larger than 50% of the area of the partition wall. Or the length of the gap is not longer than 50% of the length of the partition wall.

Abstract: An electrophoresis display with improved micro partition structure includes a control substrate having a first face and a second face, a driving circuit layer, a control electrode layer, and an electrophoresis layer. The driving circuit layer, the control electrode layer, and the electrophoresis layer are sequentially arranged on the second face. The electrophoresis layer includes a micro partition structure arranged on the control substrate and made from polymer material. The micro partition structure includes a plurality of partition walls to define chambers for accommodating a colloidal solution. The height of the partition wall of the micro partition structure is smaller than 25 um.