Abstract: A patient monitoring system may be used with catheters to monitor the infusion and drainage of any solution into the human body. The system may be used, for example, with in-dwelling catheters for peritoneal dialysis in end stage renal disease (ESRD) patients, urinary tract catheters, insulin pumps in diabetic patients, feeding tubes and central venous line catheters. The patient monitoring system includes one or more fluid pathways for infusing into and/or draining solutions out of the catheter, and one or more sensors to monitor the fluid. The patient monitoring system transmits the patient monitoring data to a database, allowing data storage, processing, and access through graphical user interfaces to patients and providers via device applications or browser-based web access portals.

Abstract: An electronic device includes: a back plate; an optical film disposed on the back plate; and a support module disposed between the back plate and the optical film, wherein the support module comprises a base and a support unit between the base and the optical film, the base comprises a curved surface away from the back plate, the support unit is connected to an upper surface of the base, and the upper surface comprises the curved surface; wherein a hollow space is enclosed by the base.

Abstract: An electronic device includes: a back plate; an optical film disposed on the back plate; and a support module disposed between the back plate and the optical film, wherein the support module includes a base, and the base includes a hollow space and a curved surface away from the back plate.

Abstract: A circuit structure for hot-press bonding includes a first substrate, a second substrate and a conductive adhesive layer. The circuit structure further includes a first conductive layer having a plurality of connection electrodes arranged on the first substrate, a second conductive layer including a plurality of backup electrodes respectively corresponding to the connection electrodes, an insulating layer arranged between the first conductive layer and the second conductive layer, and a plurality of conductive via arranged in the insulating layer and connected to corresponding connection electrodes and backup electrodes to provide current conduction paths therebetween, thus provide additional conduction path for the connection electrodes even the connection electrodes have fracture and enhance yield and connection reliability.

Abstract: A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.

Abstract: A coil structure comprises a coil and a conductive terminal part, wherein the coil is formed by a conductive wire comprising a metal wire and at least one insulating layer encapsulating the metal wire, wherein a first terminal part of the metal wire is exposed from the at least one insulating layer, wherein a first portion of the conductive terminal part encapsulates the first terminal part of the metal wire and a second portion of the conductive terminal part extends from said first portion as an electrode for electrically connecting to an external circuit.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes a first dielectric layer formed on a substrate, and two memory cells. The two memory cells include two bottom electrode structures separated from each other. Each bottom electrode structure fills one of two trenches in the first dielectric layer. The two memory cells also include a resistance switching layer and a top electrode structure. The resistance switching layer is conformally formed on the surface of an opening in the first dielectric layer, and the opening is between the two trenches. The top electrode structure is on the resistance switching layer and fills the opening. A top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure are coplanar.

Abstract: The present invention provides a probe head, comprising: an upper guide plate with a first through hole; a lower guide plate with a second through hole; and a probe structure body with a first end portion, a second end portion and a needle body. The upper guide plate and the lower guide plate jointly define an inner accommodation space. The first end portion is disposed in the first through hole, and the second end portion is disposed in the second through hole. The needle body is located between the first end portion and the second end portion, and is accommodated in the inner accommodation space. The second end portion has a fixed portion positioned on the lower guide plate, and the fixed portion has no degree of freedom to move along the penetrating direction of the second through hole. The upper section of the probe structure body relative to the fixed portion has a first spring constant, and the lower section of the probe structure body relative to the fixed portion has a second spring constant.

Abstract: A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.

Abstract: A touch control method is provided. The method includes: providing a touch device with multiple touch electrodes; determining whether an object is located in a sensing distance; detecting a sensing group sensing the object if the determination is yes; determining whether an electrode amount in the electrode group is between a first value and a second value; determining whether a sensing time of a predetermined proportion of the touch electrodes in the sensing group is equal to or greater than a predetermined time; executing a fingerprint recognition mode if the electrode amount is between the first value and the second value, and the sensing time is equal to or greater than the predetermined time; executing a touch operation mode if the electrode amount is less than the first value or greater than the second value, or the sensing time is less than the predetermined time.

Abstract: A structure of coils for a wireless charger comprises a plurality of coils, wherein the plurality of coils are stacked into a plurality of layers of coils with each layer comprising at least two coils, wherein at least two electronic devices are capable of being placed over the plurality of coils for charging the at least two electronic devices.

Abstract: Disclosed herein is a wave energy converter that uses a flexible and inflatable chamber to absorb wave energy and convert it to electrical energy through the varying hydrostatic and hydrodynamic pressure at or below the water surface.

Abstract: A memory device including a substrate, a plurality of stack structures, and a protective layer is provided. The plurality of stack structures are arranged along a first direction on an array area of the substrate, and each of the stack structures extends along a second direction different from the first direction. In a cross-sectional view of the memory device, each of the stack structures includes, in sequence from the substrate, a charge storage structure, a control gate, and a cap layer. The cap layer has a multilayer structure. The protective layer covers sidewalls of the stack structures. A width in the first direction of the charge storage structure, a width of the control gate, and a width of the cap layer are substantially equal to each other.

Abstract: A coating layer is formed on a coil made of an insulated conductive wire comprising a metal wire and an insulating layer encapsulating the metal layer, wherein the coating layer encapsulates at least one portion of the insulating layer of the insulated conductive wire so that a terminal part of the metal wire exposed from the insulating layer can be positioned firmly while going through an automatic soldering process for electrically connecting with an external circuit.

Abstract: A curve alignment method and apparatus are provided. In the method, data obtained by at least one equipment analyzing a test sample is retrieved to generate test curves. In response to an alignment operation of directing a first point around a first curve to a second point around a second curve among the test curves, a correspondence between features corresponding to the first and second points is recorded, and correspondences of alignment operations are collected as feature data. Data obtained by the equipment analyzing a current sample is retrieved to generate current curves, and a third point matching the first feature on a third curve and a fourth point matching the second feature on a fourth curve are searched according to the correspondences. At least one of the third curve and the fourth curve is adjusted to align the third point with the fourth point.

Abstract: An ribonucleic acid (RNA) detection device is disclosed, comprising a case, a substrate, at least one display component, and a processing circuit board, wherein one plane on the substrate includes an RNA detection panel and a metal mask cover covering the RNA detection panel, and, when a specimen liquid is dropped onto the RNA detection panel through the detection hole of the case and the concave opening of the metal mask cover, the signal generated by the contact of the specimen liquid with the RNA detection panel is received via the sensor circuit board thus generating the specimen signal determination value which then transferred to the processing circuit board so that the processing circuit board determines whether the specimen liquid includes the virus based on the specimen signal determination value.

Abstract: A method manufacturing of a semiconductor structure including following steps is provided. A material layer is provided. A first mask layer is formed on the material layer. Core patterns are formed on the first mask layer. A spacer material layer is conformally formed on the core patterns. An etch-back process is performed on the spacer material layer. A portion of the spacer material layer located on two ends of the core pattern is removed, then spacer structures are formed. Each spacer structure includes a merged spacer and a non-merged spacer. The core patterns are removed. The first patterned mask layer is formed to cover a portion of the merged spacer and expose another portion of the merged spacer and the non-merged spacer. The first patterned mask layer and the spacer structure are used as a mask, and the first mask layer is patterned into a second patterned mask layer.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes a first dielectric layer formed on a substrate, and two memory cells. The two memory cells include two bottom electrode structures separated from each other. Each bottom electrode structure fills one of two trenches in the first dielectric layer. The two memory cells also include a resistance switching layer and a top electrode structure. The resistance switching layer is conformity formed on the surface of an opening in the first dielectric layer, and the opening is between the two trenches. The top electrode structure is on the resistance switching layer and fills the opening. A top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure are coplanar.

Abstract: A buffer circuit is provided to output an output signal at an output node. The buffer circuit includes first and second inverters and first and second switches. The first inverter inverts an input signal. The second inverter is coupled between the first inverter and the output node. The first switch is coupled between a first voltage source terminal and the output node. The second switch is coupled between the output node and a second voltage source terminal. First and second voltages are respectively provided to the first and second voltage source terminals. In response to the input signal switching to a first level from a second level, the first switch is turned on to pre-charge the output node. In response to the input signal transiting to the second level from the first level, the second switch is turned on to pre-discharge the output node.

Abstract: A method for manufacturing a resistive random access memory structure is provided. The method includes providing a substrate, and the substrate includes an array region and a peripheral region. The method includes forming a first low-k dielectric layer in the peripheral region, and the first low-k dielectric layer has a dielectric constant of less than 3. The method includes forming a plurality of memory cells on the substrate and in the array region. The method includes forming a dummy memory cell at a boundary between the array region and the peripheral region. The method includes forming a gap-filling dielectric layer on the substrate. The method includes forming a plurality of first conductive plugs in the gap-filling dielectric layer, and each of the plurality of first conductive plugs is in contact with one of the plurality of memory cells.